392 lines
9.9 KiB
C
392 lines
9.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer
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* (C) 2005 Red Hat Inc
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* Alan Cox <alan@lxorguk.ukuu.org.uk>
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* (C) 2007,2009,2010 Bartlomiej Zolnierkiewicz
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*
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* Based in part on linux/drivers/ide/pci/pdc202xx_old.c
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*
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* First cut with LBA48/ATAPI
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*
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* TODO:
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* Channel interlock/reset on both required ?
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "pata_pdc202xx_old"
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#define DRV_VERSION "0.4.3"
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static int pdc2026x_cable_detect(struct ata_port *ap)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u16 cis;
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pci_read_config_word(pdev, 0x50, &cis);
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if (cis & (1 << (10 + ap->port_no)))
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return ATA_CBL_PATA40;
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return ATA_CBL_PATA80;
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}
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static void pdc202xx_exec_command(struct ata_port *ap,
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const struct ata_taskfile *tf)
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{
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iowrite8(tf->command, ap->ioaddr.command_addr);
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ndelay(400);
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}
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static bool pdc202xx_irq_check(struct ata_port *ap)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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unsigned long master = pci_resource_start(pdev, 4);
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u8 sc1d = inb(master + 0x1d);
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if (ap->port_no) {
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/*
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* bit 7: error, bit 6: interrupting,
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* bit 5: FIFO full, bit 4: FIFO empty
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*/
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return sc1d & 0x40;
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} else {
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/*
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* bit 3: error, bit 2: interrupting,
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* bit 1: FIFO full, bit 0: FIFO empty
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*/
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return sc1d & 0x04;
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}
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}
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/**
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* pdc202xx_configure_piomode - set chip PIO timing
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* @ap: ATA interface
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* @adev: ATA device
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* @pio: PIO mode
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*
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* Called to do the PIO mode setup. Our timing registers are shared
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* so a configure_dmamode call will undo any work we do here and vice
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* versa
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*/
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static void pdc202xx_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
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static const u16 pio_timing[5] = {
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0x0913, 0x050C , 0x0308, 0x0206, 0x0104
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};
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u8 r_ap, r_bp;
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pci_read_config_byte(pdev, port, &r_ap);
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pci_read_config_byte(pdev, port + 1, &r_bp);
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r_ap &= ~0x3F; /* Preserve ERRDY_EN, SYNC_IN */
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r_bp &= ~0x1F;
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r_ap |= (pio_timing[pio] >> 8);
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r_bp |= (pio_timing[pio] & 0xFF);
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if (ata_pio_need_iordy(adev))
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r_ap |= 0x20; /* IORDY enable */
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if (adev->class == ATA_DEV_ATA)
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r_ap |= 0x10; /* FIFO enable */
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pci_write_config_byte(pdev, port, r_ap);
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pci_write_config_byte(pdev, port + 1, r_bp);
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}
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/**
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* pdc202xx_set_piomode - set initial PIO mode data
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Called to do the PIO mode setup. Our timing registers are shared
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* but we want to set the PIO timing by default.
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*/
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static void pdc202xx_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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pdc202xx_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
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}
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/**
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* pdc202xx_set_dmamode - set DMA mode in chip
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Load DMA cycle times into the chip ready for a DMA transfer
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* to occur.
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*/
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static void pdc202xx_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
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static u8 udma_timing[6][2] = {
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{ 0x60, 0x03 }, /* 33 Mhz Clock */
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{ 0x40, 0x02 },
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{ 0x20, 0x01 },
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{ 0x40, 0x02 }, /* 66 Mhz Clock */
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{ 0x20, 0x01 },
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{ 0x20, 0x01 }
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};
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static u8 mdma_timing[3][2] = {
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{ 0xe0, 0x0f },
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{ 0x60, 0x04 },
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{ 0x60, 0x03 },
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};
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u8 r_bp, r_cp;
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pci_read_config_byte(pdev, port + 1, &r_bp);
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pci_read_config_byte(pdev, port + 2, &r_cp);
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r_bp &= ~0xE0;
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r_cp &= ~0x0F;
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if (adev->dma_mode >= XFER_UDMA_0) {
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int speed = adev->dma_mode - XFER_UDMA_0;
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r_bp |= udma_timing[speed][0];
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r_cp |= udma_timing[speed][1];
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} else {
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int speed = adev->dma_mode - XFER_MW_DMA_0;
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r_bp |= mdma_timing[speed][0];
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r_cp |= mdma_timing[speed][1];
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}
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pci_write_config_byte(pdev, port + 1, r_bp);
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pci_write_config_byte(pdev, port + 2, r_cp);
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}
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/**
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* pdc2026x_bmdma_start - DMA engine begin
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* @qc: ATA command
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*
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* In UDMA3 or higher we have to clock switch for the duration of the
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* DMA transfer sequence.
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*
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* Note: The host lock held by the libata layer protects
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* us from two channels both trying to set DMA bits at once
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*/
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static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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struct ata_device *adev = qc->dev;
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struct ata_taskfile *tf = &qc->tf;
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int sel66 = ap->port_no ? 0x08: 0x02;
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void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
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void __iomem *clock = master + 0x11;
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void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);
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u32 len;
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/* Check we keep host level locking here */
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if (adev->dma_mode > XFER_UDMA_2)
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iowrite8(ioread8(clock) | sel66, clock);
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else
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iowrite8(ioread8(clock) & ~sel66, clock);
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/* The DMA clocks may have been trashed by a reset. FIXME: make conditional
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and move to qc_issue ? */
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pdc202xx_set_dmamode(ap, qc->dev);
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/* Cases the state machine will not complete correctly without help */
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if ((tf->flags & ATA_TFLAG_LBA48) || tf->protocol == ATAPI_PROT_DMA) {
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len = qc->nbytes / 2;
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if (tf->flags & ATA_TFLAG_WRITE)
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len |= 0x06000000;
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else
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len |= 0x05000000;
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iowrite32(len, atapi_reg);
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}
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/* Activate DMA */
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ata_bmdma_start(qc);
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}
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/**
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* pdc2026x_bmdma_stop - DMA engine stop
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* @qc: ATA command
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*
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* After a DMA completes we need to put the clock back to 33MHz for
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* PIO timings.
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*
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* Note: The host lock held by the libata layer protects
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* us from two channels both trying to set DMA bits at once
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*/
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static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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struct ata_device *adev = qc->dev;
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struct ata_taskfile *tf = &qc->tf;
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int sel66 = ap->port_no ? 0x08: 0x02;
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/* The clock bits are in the same register for both channels */
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void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
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void __iomem *clock = master + 0x11;
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void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);
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/* Cases the state machine will not complete correctly */
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if (tf->protocol == ATAPI_PROT_DMA || (tf->flags & ATA_TFLAG_LBA48)) {
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iowrite32(0, atapi_reg);
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iowrite8(ioread8(clock) & ~sel66, clock);
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}
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/* Flip back to 33Mhz for PIO */
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if (adev->dma_mode > XFER_UDMA_2)
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iowrite8(ioread8(clock) & ~sel66, clock);
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ata_bmdma_stop(qc);
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pdc202xx_set_piomode(ap, adev);
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}
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/**
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* pdc2026x_dev_config - device setup hook
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* @adev: newly found device
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*
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* Perform chip specific early setup. We need to lock the transfer
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* sizes to 8bit to avoid making the state engine on the 2026x cards
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* barf.
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*/
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static void pdc2026x_dev_config(struct ata_device *adev)
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{
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adev->max_sectors = 256;
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}
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static int pdc2026x_port_start(struct ata_port *ap)
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{
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void __iomem *bmdma = ap->ioaddr.bmdma_addr;
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if (bmdma) {
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/* Enable burst mode */
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u8 burst = ioread8(bmdma + 0x1f);
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iowrite8(burst | 0x01, bmdma + 0x1f);
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}
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return ata_bmdma_port_start(ap);
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}
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/**
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* pdc2026x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
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* @qc: Metadata associated with taskfile to check
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*
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* Just say no - not supported on older Promise.
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*
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* LOCKING:
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* None (inherited from caller).
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*
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* RETURNS: 0 when ATAPI DMA can be used
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* 1 otherwise
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*/
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static int pdc2026x_check_atapi_dma(struct ata_queued_cmd *qc)
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{
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return 1;
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}
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static struct scsi_host_template pdc202xx_sht = {
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ATA_BMDMA_SHT(DRV_NAME),
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};
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static struct ata_port_operations pdc2024x_port_ops = {
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.inherits = &ata_bmdma_port_ops,
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.cable_detect = ata_cable_40wire,
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.set_piomode = pdc202xx_set_piomode,
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.set_dmamode = pdc202xx_set_dmamode,
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.sff_exec_command = pdc202xx_exec_command,
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.sff_irq_check = pdc202xx_irq_check,
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};
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static struct ata_port_operations pdc2026x_port_ops = {
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.inherits = &pdc2024x_port_ops,
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.check_atapi_dma = pdc2026x_check_atapi_dma,
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.bmdma_start = pdc2026x_bmdma_start,
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.bmdma_stop = pdc2026x_bmdma_stop,
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.cable_detect = pdc2026x_cable_detect,
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.dev_config = pdc2026x_dev_config,
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.port_start = pdc2026x_port_start,
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.sff_exec_command = pdc202xx_exec_command,
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.sff_irq_check = pdc202xx_irq_check,
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};
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static int pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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static const struct ata_port_info info[3] = {
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{
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.flags = ATA_FLAG_SLAVE_POSS,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA2,
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.port_ops = &pdc2024x_port_ops
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},
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{
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.flags = ATA_FLAG_SLAVE_POSS,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA4,
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.port_ops = &pdc2026x_port_ops
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},
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{
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.flags = ATA_FLAG_SLAVE_POSS,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA5,
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.port_ops = &pdc2026x_port_ops
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}
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};
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const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL };
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if (dev->device == PCI_DEVICE_ID_PROMISE_20265) {
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struct pci_dev *bridge = dev->bus->self;
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/* Don't grab anything behind a Promise I2O RAID */
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if (bridge && bridge->vendor == PCI_VENDOR_ID_INTEL) {
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if (bridge->device == PCI_DEVICE_ID_INTEL_I960)
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return -ENODEV;
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if (bridge->device == PCI_DEVICE_ID_INTEL_I960RM)
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return -ENODEV;
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}
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}
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return ata_pci_bmdma_init_one(dev, ppi, &pdc202xx_sht, NULL, 0);
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}
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static const struct pci_device_id pdc202xx[] = {
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{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
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{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
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{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
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{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
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{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
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{ },
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};
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static struct pci_driver pdc202xx_pci_driver = {
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.name = DRV_NAME,
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.id_table = pdc202xx,
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.probe = pdc202xx_init_one,
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.remove = ata_pci_remove_one,
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#ifdef CONFIG_PM_SLEEP
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.suspend = ata_pci_device_suspend,
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.resume = ata_pci_device_resume,
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#endif
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};
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module_pci_driver(pdc202xx_pci_driver);
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MODULE_AUTHOR("Alan Cox");
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MODULE_DESCRIPTION("low-level driver for Promise 2024x and 20262-20267");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, pdc202xx);
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MODULE_VERSION(DRV_VERSION);
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