380 lines
10 KiB
C
380 lines
10 KiB
C
/*
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* CHRP pci routines.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <asm/io.h>
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#include <asm/pgtable.h>
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#include <asm/irq.h>
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#include <asm/hydra.h>
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#include <asm/prom.h>
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#include <asm/machdep.h>
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#include <asm/sections.h>
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#include <asm/pci-bridge.h>
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#include <asm/grackle.h>
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#include <asm/rtas.h>
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#include "chrp.h"
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#include "gg2.h"
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/* LongTrail */
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void __iomem *gg2_pci_config_base;
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/*
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* The VLSI Golden Gate II has only 512K of PCI configuration space, so we
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* limit the bus number to 3 bits
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*/
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int gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off,
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int len, u32 *val)
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{
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volatile void __iomem *cfg_data;
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struct pci_controller *hose = pci_bus_to_host(bus);
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if (bus->number > 7)
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* Note: the caller has already checked that off is
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* suitably aligned and that len is 1, 2 or 4.
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*/
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cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off);
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switch (len) {
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case 1:
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*val = in_8(cfg_data);
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break;
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case 2:
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*val = in_le16(cfg_data);
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break;
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default:
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*val = in_le32(cfg_data);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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int gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off,
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int len, u32 val)
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{
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volatile void __iomem *cfg_data;
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struct pci_controller *hose = pci_bus_to_host(bus);
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if (bus->number > 7)
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* Note: the caller has already checked that off is
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* suitably aligned and that len is 1, 2 or 4.
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*/
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cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off);
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switch (len) {
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case 1:
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out_8(cfg_data, val);
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break;
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case 2:
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out_le16(cfg_data, val);
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break;
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default:
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out_le32(cfg_data, val);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops gg2_pci_ops =
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{
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.read = gg2_read_config,
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.write = gg2_write_config,
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};
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/*
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* Access functions for PCI config space using RTAS calls.
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*/
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int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
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int len, u32 *val)
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{
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struct pci_controller *hose = pci_bus_to_host(bus);
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unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
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| (((bus->number - hose->first_busno) & 0xff) << 16)
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| (hose->global_number << 24);
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int ret = -1;
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int rval;
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rval = rtas_call(rtas_token("read-pci-config"), 2, 2, &ret, addr, len);
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*val = ret;
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return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
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}
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int rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
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int len, u32 val)
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{
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struct pci_controller *hose = pci_bus_to_host(bus);
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unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
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| (((bus->number - hose->first_busno) & 0xff) << 16)
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| (hose->global_number << 24);
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int rval;
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rval = rtas_call(rtas_token("write-pci-config"), 3, 1, NULL,
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addr, len, val);
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return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops rtas_pci_ops =
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{
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.read = rtas_read_config,
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.write = rtas_write_config,
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};
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volatile struct Hydra __iomem *Hydra = NULL;
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int __init
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hydra_init(void)
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{
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struct device_node *np;
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struct resource r;
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np = of_find_node_by_name(NULL, "mac-io");
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if (np == NULL || of_address_to_resource(np, 0, &r)) {
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of_node_put(np);
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return 0;
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}
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of_node_put(np);
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Hydra = ioremap(r.start, r.end-r.start);
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printk("Hydra Mac I/O at %llx\n", (unsigned long long)r.start);
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printk("Hydra Feature_Control was %x",
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in_le32(&Hydra->Feature_Control));
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out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN |
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HYDRA_FC_SCSI_CELL_EN |
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HYDRA_FC_SCCA_ENABLE |
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HYDRA_FC_SCCB_ENABLE |
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HYDRA_FC_ARB_BYPASS |
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HYDRA_FC_MPIC_ENABLE |
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HYDRA_FC_SLOW_SCC_PCLK |
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HYDRA_FC_MPIC_IS_MASTER));
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printk(", now %x\n", in_le32(&Hydra->Feature_Control));
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return 1;
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}
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#define PRG_CL_RESET_VALID 0x00010000
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static void __init
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setup_python(struct pci_controller *hose, struct device_node *dev)
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{
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u32 __iomem *reg;
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u32 val;
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struct resource r;
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if (of_address_to_resource(dev, 0, &r)) {
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printk(KERN_ERR "No address for Python PCI controller\n");
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return;
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}
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/* Clear the magic go-slow bit */
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reg = ioremap(r.start + 0xf6000, 0x40);
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BUG_ON(!reg);
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val = in_be32(®[12]);
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if (val & PRG_CL_RESET_VALID) {
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out_be32(®[12], val & ~PRG_CL_RESET_VALID);
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in_be32(®[12]);
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}
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iounmap(reg);
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setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010, 0);
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}
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/* Marvell Discovery II based Pegasos 2 */
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static void __init setup_peg2(struct pci_controller *hose, struct device_node *dev)
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{
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struct device_node *root = of_find_node_by_path("/");
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struct device_node *rtas;
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rtas = of_find_node_by_name (root, "rtas");
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if (rtas) {
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hose->ops = &rtas_pci_ops;
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of_node_put(rtas);
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} else {
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printk ("RTAS supporting Pegasos OF not found, please upgrade"
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" your firmware\n");
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}
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ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS);
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/* keep the reference to the root node */
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}
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void __init
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chrp_find_bridges(void)
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{
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struct device_node *dev;
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const int *bus_range;
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int len, index = -1;
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struct pci_controller *hose;
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const unsigned int *dma;
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const char *model, *machine;
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int is_longtrail = 0, is_mot = 0, is_pegasos = 0;
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struct device_node *root = of_find_node_by_path("/");
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struct resource r;
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/*
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* The PCI host bridge nodes on some machines don't have
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* properties to adequately identify them, so we have to
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* look at what sort of machine this is as well.
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*/
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machine = of_get_property(root, "model", NULL);
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if (machine != NULL) {
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is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0;
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is_mot = strncmp(machine, "MOT", 3) == 0;
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if (strncmp(machine, "Pegasos2", 8) == 0)
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is_pegasos = 2;
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else if (strncmp(machine, "Pegasos", 7) == 0)
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is_pegasos = 1;
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}
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for (dev = root->child; dev != NULL; dev = dev->sibling) {
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if (dev->type == NULL || strcmp(dev->type, "pci") != 0)
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continue;
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++index;
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/* The GG2 bridge on the LongTrail doesn't have an address */
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if (of_address_to_resource(dev, 0, &r) && !is_longtrail) {
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printk(KERN_WARNING "Can't use %s: no address\n",
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dev->full_name);
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continue;
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}
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bus_range = of_get_property(dev, "bus-range", &len);
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if (bus_range == NULL || len < 2 * sizeof(int)) {
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printk(KERN_WARNING "Can't get bus-range for %s\n",
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dev->full_name);
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continue;
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}
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if (bus_range[1] == bus_range[0])
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printk(KERN_INFO "PCI bus %d", bus_range[0]);
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else
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printk(KERN_INFO "PCI buses %d..%d",
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bus_range[0], bus_range[1]);
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printk(" controlled by %s", dev->full_name);
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if (!is_longtrail)
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printk(" at %llx", (unsigned long long)r.start);
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printk("\n");
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hose = pcibios_alloc_controller(dev);
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if (!hose) {
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printk("Can't allocate PCI controller structure for %s\n",
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dev->full_name);
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continue;
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}
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hose->first_busno = hose->self_busno = bus_range[0];
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hose->last_busno = bus_range[1];
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model = of_get_property(dev, "model", NULL);
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if (model == NULL)
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model = "<none>";
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if (strncmp(model, "IBM, Python", 11) == 0) {
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setup_python(hose, dev);
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} else if (is_mot
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|| strncmp(model, "Motorola, Grackle", 17) == 0) {
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setup_grackle(hose);
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} else if (is_longtrail) {
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void __iomem *p = ioremap(GG2_PCI_CONFIG_BASE, 0x80000);
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hose->ops = &gg2_pci_ops;
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hose->cfg_data = p;
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gg2_pci_config_base = p;
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} else if (is_pegasos == 1) {
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setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc, 0);
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} else if (is_pegasos == 2) {
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setup_peg2(hose, dev);
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} else if (!strncmp(model, "IBM,CPC710", 10)) {
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setup_indirect_pci(hose,
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r.start + 0x000f8000,
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r.start + 0x000f8010,
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0);
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if (index == 0) {
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dma = of_get_property(dev, "system-dma-base",
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&len);
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if (dma && len >= sizeof(*dma)) {
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dma = (unsigned int *)
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(((unsigned long)dma) +
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len - sizeof(*dma));
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pci_dram_offset = *dma;
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}
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}
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} else {
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printk("No methods for %s (model %s), using RTAS\n",
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dev->full_name, model);
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hose->ops = &rtas_pci_ops;
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}
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pci_process_bridge_OF_ranges(hose, dev, index == 0);
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/* check the first bridge for a property that we can
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use to set pci_dram_offset */
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dma = of_get_property(dev, "ibm,dma-ranges", &len);
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if (index == 0 && dma != NULL && len >= 6 * sizeof(*dma)) {
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pci_dram_offset = dma[2] - dma[3];
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printk("pci_dram_offset = %lx\n", pci_dram_offset);
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}
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}
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of_node_put(root);
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}
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/* SL82C105 IDE Control/Status Register */
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#define SL82C105_IDECSR 0x40
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/* Fixup for Winbond ATA quirk, required for briq mostly because the
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* 8259 is configured for level sensitive IRQ 14 and so wants the
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* ATA controller to be set to fully native mode or bad things
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* will happen.
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*/
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static void __devinit chrp_pci_fixup_winbond_ata(struct pci_dev *sl82c105)
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{
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u8 progif;
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/* If non-briq machines need that fixup too, please speak up */
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if (!machine_is(chrp) || _chrp_type != _CHRP_briq)
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return;
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if ((sl82c105->class & 5) != 5) {
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printk("W83C553: Switching SL82C105 IDE to PCI native mode\n");
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/* Enable SL82C105 PCI native IDE mode */
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pci_read_config_byte(sl82c105, PCI_CLASS_PROG, &progif);
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pci_write_config_byte(sl82c105, PCI_CLASS_PROG, progif | 0x05);
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sl82c105->class |= 0x05;
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/* Disable SL82C105 second port */
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pci_write_config_word(sl82c105, SL82C105_IDECSR, 0x0003);
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/* Clear IO BARs, they will be reassigned */
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pci_write_config_dword(sl82c105, PCI_BASE_ADDRESS_0, 0);
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pci_write_config_dword(sl82c105, PCI_BASE_ADDRESS_1, 0);
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pci_write_config_dword(sl82c105, PCI_BASE_ADDRESS_2, 0);
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pci_write_config_dword(sl82c105, PCI_BASE_ADDRESS_3, 0);
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}
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105,
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chrp_pci_fixup_winbond_ata);
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/* Pegasos2 firmware version 20040810 configures the built-in IDE controller
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* in legacy mode, but sets the PCI registers to PCI native mode.
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* The chip can only operate in legacy mode, so force the PCI class into legacy
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* mode as well. The same fixup must be done to the class-code property in
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* the IDE node /pci@80000000/ide@C,1
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*/
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static void chrp_pci_fixup_vt8231_ata(struct pci_dev *viaide)
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{
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u8 progif;
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struct pci_dev *viaisa;
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if (!machine_is(chrp) || _chrp_type != _CHRP_Pegasos)
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return;
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if (viaide->irq != 14)
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return;
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viaisa = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
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if (!viaisa)
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return;
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dev_info(&viaide->dev, "Fixing VIA IDE, force legacy mode on\n");
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pci_read_config_byte(viaide, PCI_CLASS_PROG, &progif);
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pci_write_config_byte(viaide, PCI_CLASS_PROG, progif & ~0x5);
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viaide->class &= ~0x5;
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pci_dev_put(viaisa);
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, chrp_pci_fixup_vt8231_ata);
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