150 lines
3.8 KiB
C
150 lines
3.8 KiB
C
/*
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* Freescale eSDHC i.MX controller driver for the platform bus.
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*
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* derived from the OF-version.
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*
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* Copyright (c) 2010 Pengutronix e.K.
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* Author: Wolfram Sang <w.sang@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License.
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*/
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/sdhci-pltfm.h>
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#include <mach/hardware.h>
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#include "sdhci.h"
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#include "sdhci-pltfm.h"
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#include "sdhci-esdhc.h"
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static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
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{
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void __iomem *base = host->ioaddr + (reg & ~0x3);
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u32 shift = (reg & 0x3) * 8;
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writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
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}
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static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
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{
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if (unlikely(reg == SDHCI_HOST_VERSION))
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reg ^= 2;
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return readw(host->ioaddr + reg);
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}
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static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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switch (reg) {
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case SDHCI_TRANSFER_MODE:
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/*
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* Postpone this write, we must do it together with a
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* command write that is down below.
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*/
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pltfm_host->scratchpad = val;
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return;
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case SDHCI_COMMAND:
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writel(val << 16 | pltfm_host->scratchpad,
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host->ioaddr + SDHCI_TRANSFER_MODE);
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return;
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case SDHCI_BLOCK_SIZE:
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val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
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break;
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}
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esdhc_clrset_le(host, 0xffff, val, reg);
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}
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static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
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{
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u32 new_val;
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switch (reg) {
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case SDHCI_POWER_CONTROL:
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/*
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* FSL put some DMA bits here
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* If your board has a regulator, code should be here
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*/
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return;
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case SDHCI_HOST_CONTROL:
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/* FSL messed up here, so we can just keep those two */
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new_val = val & (SDHCI_CTRL_LED | SDHCI_CTRL_4BITBUS);
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/* ensure the endianess */
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new_val |= ESDHC_HOST_CONTROL_LE;
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/* DMA mode bits are shifted */
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new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
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esdhc_clrset_le(host, 0xffff, new_val, reg);
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return;
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}
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esdhc_clrset_le(host, 0xff, val, reg);
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}
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static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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return clk_get_rate(pltfm_host->clk);
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}
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static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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return clk_get_rate(pltfm_host->clk) / 256 / 16;
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}
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static int esdhc_pltfm_init(struct sdhci_host *host, struct sdhci_pltfm_data *pdata)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct clk *clk;
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clk = clk_get(mmc_dev(host->mmc), NULL);
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if (IS_ERR(clk)) {
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dev_err(mmc_dev(host->mmc), "clk err\n");
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return PTR_ERR(clk);
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}
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clk_enable(clk);
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pltfm_host->clk = clk;
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if (cpu_is_mx35() || cpu_is_mx51())
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host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
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/* Fix errata ENGcm07207 which is present on i.MX25 and i.MX35 */
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if (cpu_is_mx25() || cpu_is_mx35())
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host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK;
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return 0;
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}
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static void esdhc_pltfm_exit(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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clk_disable(pltfm_host->clk);
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clk_put(pltfm_host->clk);
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}
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static struct sdhci_ops sdhci_esdhc_ops = {
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.read_w = esdhc_readw_le,
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.write_w = esdhc_writew_le,
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.write_b = esdhc_writeb_le,
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.set_clock = esdhc_set_clock,
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.get_max_clock = esdhc_pltfm_get_max_clock,
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.get_min_clock = esdhc_pltfm_get_min_clock,
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};
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struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
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.quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_ADMA,
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/* ADMA has issues. Might be fixable */
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.ops = &sdhci_esdhc_ops,
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.init = esdhc_pltfm_init,
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.exit = esdhc_pltfm_exit,
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};
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