642 lines
13 KiB
C
642 lines
13 KiB
C
#include <linux/interrupt.h>
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#include <linux/dmar.h>
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#include <linux/spinlock.h>
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#include <linux/jiffies.h>
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#include <linux/pci.h>
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#include <linux/irq.h>
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#include <asm/io_apic.h>
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#include <asm/smp.h>
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#include <asm/cpu.h>
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#include <linux/intel-iommu.h>
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#include "intr_remapping.h"
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static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
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static int ir_ioapic_num;
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int intr_remapping_enabled;
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struct irq_2_iommu {
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struct intel_iommu *iommu;
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u16 irte_index;
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u16 sub_handle;
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u8 irte_mask;
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};
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#ifdef CONFIG_GENERIC_HARDIRQS
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static struct irq_2_iommu *get_one_free_irq_2_iommu(int cpu)
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{
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struct irq_2_iommu *iommu;
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int node;
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node = cpu_to_node(cpu);
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iommu = kzalloc_node(sizeof(*iommu), GFP_ATOMIC, node);
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printk(KERN_DEBUG "alloc irq_2_iommu on cpu %d node %d\n", cpu, node);
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return iommu;
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}
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static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
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{
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struct irq_desc *desc;
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desc = irq_to_desc(irq);
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if (WARN_ON_ONCE(!desc))
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return NULL;
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return desc->irq_2_iommu;
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}
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static struct irq_2_iommu *irq_2_iommu_alloc_cpu(unsigned int irq, int cpu)
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{
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struct irq_desc *desc;
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struct irq_2_iommu *irq_iommu;
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/*
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* alloc irq desc if not allocated already.
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*/
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desc = irq_to_desc_alloc_cpu(irq, cpu);
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if (!desc) {
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printk(KERN_INFO "can not get irq_desc for %d\n", irq);
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return NULL;
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}
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irq_iommu = desc->irq_2_iommu;
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if (!irq_iommu)
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desc->irq_2_iommu = get_one_free_irq_2_iommu(cpu);
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return desc->irq_2_iommu;
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}
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static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq)
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{
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return irq_2_iommu_alloc_cpu(irq, boot_cpu_id);
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}
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#else /* !CONFIG_SPARSE_IRQ */
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static struct irq_2_iommu irq_2_iommuX[NR_IRQS];
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static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
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{
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if (irq < nr_irqs)
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return &irq_2_iommuX[irq];
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return NULL;
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}
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static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq)
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{
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return irq_2_iommu(irq);
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}
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#endif
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static DEFINE_SPINLOCK(irq_2_ir_lock);
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static struct irq_2_iommu *valid_irq_2_iommu(unsigned int irq)
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{
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struct irq_2_iommu *irq_iommu;
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irq_iommu = irq_2_iommu(irq);
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if (!irq_iommu)
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return NULL;
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if (!irq_iommu->iommu)
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return NULL;
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return irq_iommu;
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}
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int irq_remapped(int irq)
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{
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return valid_irq_2_iommu(irq) != NULL;
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}
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int get_irte(int irq, struct irte *entry)
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{
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int index;
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struct irq_2_iommu *irq_iommu;
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unsigned long flags;
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if (!entry)
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return -1;
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spin_lock_irqsave(&irq_2_ir_lock, flags);
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irq_iommu = valid_irq_2_iommu(irq);
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if (!irq_iommu) {
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spin_unlock_irqrestore(&irq_2_ir_lock, flags);
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return -1;
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}
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index = irq_iommu->irte_index + irq_iommu->sub_handle;
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*entry = *(irq_iommu->iommu->ir_table->base + index);
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spin_unlock_irqrestore(&irq_2_ir_lock, flags);
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return 0;
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}
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int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
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{
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struct ir_table *table = iommu->ir_table;
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struct irq_2_iommu *irq_iommu;
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u16 index, start_index;
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unsigned int mask = 0;
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unsigned long flags;
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int i;
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if (!count)
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return -1;
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#ifndef CONFIG_SPARSE_IRQ
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/* protect irq_2_iommu_alloc later */
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if (irq >= nr_irqs)
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return -1;
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#endif
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/*
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* start the IRTE search from index 0.
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*/
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index = start_index = 0;
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if (count > 1) {
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count = __roundup_pow_of_two(count);
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mask = ilog2(count);
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}
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if (mask > ecap_max_handle_mask(iommu->ecap)) {
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printk(KERN_ERR
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"Requested mask %x exceeds the max invalidation handle"
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" mask value %Lx\n", mask,
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ecap_max_handle_mask(iommu->ecap));
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return -1;
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}
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spin_lock_irqsave(&irq_2_ir_lock, flags);
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do {
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for (i = index; i < index + count; i++)
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if (table->base[i].present)
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break;
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/* empty index found */
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if (i == index + count)
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break;
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index = (index + count) % INTR_REMAP_TABLE_ENTRIES;
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if (index == start_index) {
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spin_unlock_irqrestore(&irq_2_ir_lock, flags);
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printk(KERN_ERR "can't allocate an IRTE\n");
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return -1;
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}
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} while (1);
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for (i = index; i < index + count; i++)
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table->base[i].present = 1;
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irq_iommu = irq_2_iommu_alloc(irq);
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if (!irq_iommu) {
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spin_unlock_irqrestore(&irq_2_ir_lock, flags);
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printk(KERN_ERR "can't allocate irq_2_iommu\n");
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return -1;
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}
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irq_iommu->iommu = iommu;
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irq_iommu->irte_index = index;
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irq_iommu->sub_handle = 0;
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irq_iommu->irte_mask = mask;
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spin_unlock_irqrestore(&irq_2_ir_lock, flags);
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return index;
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}
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static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
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{
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struct qi_desc desc;
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desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
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| QI_IEC_SELECTIVE;
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desc.high = 0;
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return qi_submit_sync(&desc, iommu);
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}
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int map_irq_to_irte_handle(int irq, u16 *sub_handle)
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{
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int index;
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struct irq_2_iommu *irq_iommu;
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unsigned long flags;
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spin_lock_irqsave(&irq_2_ir_lock, flags);
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irq_iommu = valid_irq_2_iommu(irq);
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if (!irq_iommu) {
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spin_unlock_irqrestore(&irq_2_ir_lock, flags);
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return -1;
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}
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*sub_handle = irq_iommu->sub_handle;
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index = irq_iommu->irte_index;
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spin_unlock_irqrestore(&irq_2_ir_lock, flags);
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return index;
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}
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int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle)
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{
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struct irq_2_iommu *irq_iommu;
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unsigned long flags;
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spin_lock_irqsave(&irq_2_ir_lock, flags);
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irq_iommu = irq_2_iommu_alloc(irq);
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if (!irq_iommu) {
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spin_unlock_irqrestore(&irq_2_ir_lock, flags);
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printk(KERN_ERR "can't allocate irq_2_iommu\n");
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return -1;
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}
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irq_iommu->iommu = iommu;
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irq_iommu->irte_index = index;
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irq_iommu->sub_handle = subhandle;
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irq_iommu->irte_mask = 0;
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spin_unlock_irqrestore(&irq_2_ir_lock, flags);
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return 0;
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}
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int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index)
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{
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struct irq_2_iommu *irq_iommu;
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unsigned long flags;
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spin_lock_irqsave(&irq_2_ir_lock, flags);
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irq_iommu = valid_irq_2_iommu(irq);
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if (!irq_iommu) {
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spin_unlock_irqrestore(&irq_2_ir_lock, flags);
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return -1;
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}
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irq_iommu->iommu = NULL;
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irq_iommu->irte_index = 0;
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irq_iommu->sub_handle = 0;
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irq_2_iommu(irq)->irte_mask = 0;
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spin_unlock_irqrestore(&irq_2_ir_lock, flags);
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return 0;
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}
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int modify_irte(int irq, struct irte *irte_modified)
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{
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int rc;
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int index;
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struct irte *irte;
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struct intel_iommu *iommu;
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struct irq_2_iommu *irq_iommu;
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unsigned long flags;
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spin_lock_irqsave(&irq_2_ir_lock, flags);
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irq_iommu = valid_irq_2_iommu(irq);
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if (!irq_iommu) {
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spin_unlock_irqrestore(&irq_2_ir_lock, flags);
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return -1;
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}
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iommu = irq_iommu->iommu;
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index = irq_iommu->irte_index + irq_iommu->sub_handle;
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irte = &iommu->ir_table->base[index];
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set_64bit((unsigned long *)irte, irte_modified->low);
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__iommu_flush_cache(iommu, irte, sizeof(*irte));
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rc = qi_flush_iec(iommu, index, 0);
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spin_unlock_irqrestore(&irq_2_ir_lock, flags);
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return rc;
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}
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int flush_irte(int irq)
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{
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int rc;
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int index;
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struct intel_iommu *iommu;
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struct irq_2_iommu *irq_iommu;
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unsigned long flags;
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spin_lock_irqsave(&irq_2_ir_lock, flags);
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irq_iommu = valid_irq_2_iommu(irq);
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if (!irq_iommu) {
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spin_unlock_irqrestore(&irq_2_ir_lock, flags);
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return -1;
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}
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iommu = irq_iommu->iommu;
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index = irq_iommu->irte_index + irq_iommu->sub_handle;
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rc = qi_flush_iec(iommu, index, irq_iommu->irte_mask);
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spin_unlock_irqrestore(&irq_2_ir_lock, flags);
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return rc;
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}
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struct intel_iommu *map_ioapic_to_ir(int apic)
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{
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int i;
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for (i = 0; i < MAX_IO_APICS; i++)
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if (ir_ioapic[i].id == apic)
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return ir_ioapic[i].iommu;
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return NULL;
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}
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struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
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{
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struct dmar_drhd_unit *drhd;
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drhd = dmar_find_matched_drhd_unit(dev);
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if (!drhd)
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return NULL;
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return drhd->iommu;
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}
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int free_irte(int irq)
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{
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int rc = 0;
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int index, i;
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struct irte *irte;
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struct intel_iommu *iommu;
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struct irq_2_iommu *irq_iommu;
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unsigned long flags;
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spin_lock_irqsave(&irq_2_ir_lock, flags);
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irq_iommu = valid_irq_2_iommu(irq);
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if (!irq_iommu) {
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spin_unlock_irqrestore(&irq_2_ir_lock, flags);
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return -1;
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}
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iommu = irq_iommu->iommu;
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index = irq_iommu->irte_index + irq_iommu->sub_handle;
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irte = &iommu->ir_table->base[index];
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if (!irq_iommu->sub_handle) {
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for (i = 0; i < (1 << irq_iommu->irte_mask); i++)
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set_64bit((unsigned long *)(irte + i), 0);
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rc = qi_flush_iec(iommu, index, irq_iommu->irte_mask);
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}
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irq_iommu->iommu = NULL;
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irq_iommu->irte_index = 0;
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irq_iommu->sub_handle = 0;
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irq_iommu->irte_mask = 0;
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spin_unlock_irqrestore(&irq_2_ir_lock, flags);
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return rc;
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}
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static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
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{
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u64 addr;
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u32 cmd, sts;
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unsigned long flags;
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addr = virt_to_phys((void *)iommu->ir_table->base);
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spin_lock_irqsave(&iommu->register_lock, flags);
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dmar_writeq(iommu->reg + DMAR_IRTA_REG,
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(addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
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/* Set interrupt-remapping table pointer */
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cmd = iommu->gcmd | DMA_GCMD_SIRTP;
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writel(cmd, iommu->reg + DMAR_GCMD_REG);
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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readl, (sts & DMA_GSTS_IRTPS), sts);
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spin_unlock_irqrestore(&iommu->register_lock, flags);
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/*
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* global invalidation of interrupt entry cache before enabling
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* interrupt-remapping.
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*/
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qi_global_iec(iommu);
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spin_lock_irqsave(&iommu->register_lock, flags);
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/* Enable interrupt-remapping */
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cmd = iommu->gcmd | DMA_GCMD_IRE;
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iommu->gcmd |= DMA_GCMD_IRE;
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writel(cmd, iommu->reg + DMAR_GCMD_REG);
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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readl, (sts & DMA_GSTS_IRES), sts);
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spin_unlock_irqrestore(&iommu->register_lock, flags);
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}
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static int setup_intr_remapping(struct intel_iommu *iommu, int mode)
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{
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struct ir_table *ir_table;
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struct page *pages;
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ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table),
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GFP_ATOMIC);
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if (!iommu->ir_table)
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return -ENOMEM;
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pages = alloc_pages(GFP_ATOMIC | __GFP_ZERO, INTR_REMAP_PAGE_ORDER);
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if (!pages) {
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printk(KERN_ERR "failed to allocate pages of order %d\n",
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INTR_REMAP_PAGE_ORDER);
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kfree(iommu->ir_table);
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return -ENOMEM;
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}
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ir_table->base = page_address(pages);
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iommu_set_intr_remapping(iommu, mode);
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return 0;
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}
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/*
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* Disable Interrupt Remapping.
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*/
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static void disable_intr_remapping(struct intel_iommu *iommu)
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{
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unsigned long flags;
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u32 sts;
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if (!ecap_ir_support(iommu->ecap))
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return;
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spin_lock_irqsave(&iommu->register_lock, flags);
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sts = dmar_readq(iommu->reg + DMAR_GSTS_REG);
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if (!(sts & DMA_GSTS_IRES))
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goto end;
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iommu->gcmd &= ~DMA_GCMD_IRE;
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writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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readl, !(sts & DMA_GSTS_IRES), sts);
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end:
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spin_unlock_irqrestore(&iommu->register_lock, flags);
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}
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int __init enable_intr_remapping(int eim)
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{
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struct dmar_drhd_unit *drhd;
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int setup = 0;
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for_each_drhd_unit(drhd) {
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struct intel_iommu *iommu = drhd->iommu;
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/*
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* Clear previous faults.
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*/
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dmar_fault(-1, iommu);
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/*
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* Disable intr remapping and queued invalidation, if already
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* enabled prior to OS handover.
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*/
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disable_intr_remapping(iommu);
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dmar_disable_qi(iommu);
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}
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/*
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* check for the Interrupt-remapping support
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*/
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for_each_drhd_unit(drhd) {
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struct intel_iommu *iommu = drhd->iommu;
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if (!ecap_ir_support(iommu->ecap))
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continue;
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if (eim && !ecap_eim_support(iommu->ecap)) {
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printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, "
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" ecap %Lx\n", drhd->reg_base_addr, iommu->ecap);
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return -1;
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}
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}
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/*
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* Enable queued invalidation for all the DRHD's.
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*/
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for_each_drhd_unit(drhd) {
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int ret;
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|
struct intel_iommu *iommu = drhd->iommu;
|
|
ret = dmar_enable_qi(iommu);
|
|
|
|
if (ret) {
|
|
printk(KERN_ERR "DRHD %Lx: failed to enable queued, "
|
|
" invalidation, ecap %Lx, ret %d\n",
|
|
drhd->reg_base_addr, iommu->ecap, ret);
|
|
return -1;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Setup Interrupt-remapping for all the DRHD's now.
|
|
*/
|
|
for_each_drhd_unit(drhd) {
|
|
struct intel_iommu *iommu = drhd->iommu;
|
|
|
|
if (!ecap_ir_support(iommu->ecap))
|
|
continue;
|
|
|
|
if (setup_intr_remapping(iommu, eim))
|
|
goto error;
|
|
|
|
setup = 1;
|
|
}
|
|
|
|
if (!setup)
|
|
goto error;
|
|
|
|
intr_remapping_enabled = 1;
|
|
|
|
return 0;
|
|
|
|
error:
|
|
/*
|
|
* handle error condition gracefully here!
|
|
*/
|
|
return -1;
|
|
}
|
|
|
|
static int ir_parse_ioapic_scope(struct acpi_dmar_header *header,
|
|
struct intel_iommu *iommu)
|
|
{
|
|
struct acpi_dmar_hardware_unit *drhd;
|
|
struct acpi_dmar_device_scope *scope;
|
|
void *start, *end;
|
|
|
|
drhd = (struct acpi_dmar_hardware_unit *)header;
|
|
|
|
start = (void *)(drhd + 1);
|
|
end = ((void *)drhd) + header->length;
|
|
|
|
while (start < end) {
|
|
scope = start;
|
|
if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) {
|
|
if (ir_ioapic_num == MAX_IO_APICS) {
|
|
printk(KERN_WARNING "Exceeded Max IO APICS\n");
|
|
return -1;
|
|
}
|
|
|
|
printk(KERN_INFO "IOAPIC id %d under DRHD base"
|
|
" 0x%Lx\n", scope->enumeration_id,
|
|
drhd->address);
|
|
|
|
ir_ioapic[ir_ioapic_num].iommu = iommu;
|
|
ir_ioapic[ir_ioapic_num].id = scope->enumeration_id;
|
|
ir_ioapic_num++;
|
|
}
|
|
start += scope->length;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Finds the assocaition between IOAPIC's and its Interrupt-remapping
|
|
* hardware unit.
|
|
*/
|
|
int __init parse_ioapics_under_ir(void)
|
|
{
|
|
struct dmar_drhd_unit *drhd;
|
|
int ir_supported = 0;
|
|
|
|
for_each_drhd_unit(drhd) {
|
|
struct intel_iommu *iommu = drhd->iommu;
|
|
|
|
if (ecap_ir_support(iommu->ecap)) {
|
|
if (ir_parse_ioapic_scope(drhd->hdr, iommu))
|
|
return -1;
|
|
|
|
ir_supported = 1;
|
|
}
|
|
}
|
|
|
|
if (ir_supported && ir_ioapic_num != nr_ioapics) {
|
|
printk(KERN_WARNING
|
|
"Not all IO-APIC's listed under remapping hardware\n");
|
|
return -1;
|
|
}
|
|
|
|
return ir_supported;
|
|
}
|