166 lines
3.9 KiB
C
166 lines
3.9 KiB
C
/*
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* Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include <linux/device.h>
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#include <linux/kobject.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/io.h>
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#include <soc/tegra/common.h>
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#include <soc/tegra/fuse.h>
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#include "fuse.h"
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static u32 (*fuse_readl)(const unsigned int offset);
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static int fuse_size;
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struct tegra_sku_info tegra_sku_info;
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EXPORT_SYMBOL(tegra_sku_info);
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static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
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[TEGRA_REVISION_UNKNOWN] = "unknown",
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[TEGRA_REVISION_A01] = "A01",
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[TEGRA_REVISION_A02] = "A02",
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[TEGRA_REVISION_A03] = "A03",
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[TEGRA_REVISION_A03p] = "A03 prime",
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[TEGRA_REVISION_A04] = "A04",
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};
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static u8 fuse_readb(const unsigned int offset)
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{
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u32 val;
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val = fuse_readl(round_down(offset, 4));
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val >>= (offset % 4) * 8;
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val &= 0xff;
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return val;
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}
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static ssize_t fuse_read(struct file *fd, struct kobject *kobj,
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struct bin_attribute *attr, char *buf,
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loff_t pos, size_t size)
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{
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int i;
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if (pos < 0 || pos >= fuse_size)
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return 0;
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if (size > fuse_size - pos)
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size = fuse_size - pos;
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for (i = 0; i < size; i++)
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buf[i] = fuse_readb(pos + i);
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return i;
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}
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static struct bin_attribute fuse_bin_attr = {
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.attr = { .name = "fuse", .mode = S_IRUGO, },
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.read = fuse_read,
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};
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static const struct of_device_id car_match[] __initconst = {
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{ .compatible = "nvidia,tegra20-car", },
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{ .compatible = "nvidia,tegra30-car", },
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{ .compatible = "nvidia,tegra114-car", },
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{ .compatible = "nvidia,tegra124-car", },
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{ .compatible = "nvidia,tegra132-car", },
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{},
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};
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static void tegra_enable_fuse_clk(void __iomem *base)
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{
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u32 reg;
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reg = readl_relaxed(base + 0x48);
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reg |= 1 << 28;
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writel(reg, base + 0x48);
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/*
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* Enable FUSE clock. This needs to be hardcoded because the clock
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* subsystem is not active during early boot.
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*/
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reg = readl(base + 0x14);
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reg |= 1 << 7;
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writel(reg, base + 0x14);
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}
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int tegra_fuse_readl(unsigned long offset, u32 *value)
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{
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if (!fuse_readl)
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return -EPROBE_DEFER;
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*value = fuse_readl(offset);
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return 0;
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}
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EXPORT_SYMBOL(tegra_fuse_readl);
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int tegra_fuse_create_sysfs(struct device *dev, int size,
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u32 (*readl)(const unsigned int offset))
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{
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if (fuse_size)
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return -ENODEV;
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fuse_bin_attr.size = size;
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fuse_bin_attr.read = fuse_read;
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fuse_size = size;
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fuse_readl = readl;
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return device_create_bin_file(dev, &fuse_bin_attr);
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}
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static int __init tegra_init_fuse(void)
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{
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struct device_node *np;
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void __iomem *car_base;
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if (!soc_is_tegra())
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return 0;
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tegra_init_apbmisc();
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np = of_find_matching_node(NULL, car_match);
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car_base = of_iomap(np, 0);
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if (car_base) {
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tegra_enable_fuse_clk(car_base);
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iounmap(car_base);
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} else {
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pr_err("Could not enable fuse clk. ioremap tegra car failed.\n");
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return -ENXIO;
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}
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if (tegra_get_chip_id() == TEGRA20)
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tegra20_init_fuse_early();
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else
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tegra30_init_fuse_early();
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pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
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tegra_revision_name[tegra_sku_info.revision],
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tegra_sku_info.sku_id, tegra_sku_info.cpu_process_id,
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tegra_sku_info.core_process_id);
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pr_debug("Tegra CPU Speedo ID %d, Soc Speedo ID %d\n",
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tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id);
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return 0;
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}
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early_initcall(tegra_init_fuse);
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