537 lines
12 KiB
Plaintext
537 lines
12 KiB
Plaintext
#
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# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License version 2 as
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# published by the Free Software Foundation.
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#
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config ARC
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def_bool y
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select BUILDTIME_EXTABLE_SORT
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select COMMON_CLK
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select CLONE_BACKWARDS
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# ARC Busybox based initramfs absolutely relies on DEVTMPFS for /dev
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select DEVTMPFS if !INITRAMFS_SOURCE=""
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select GENERIC_ATOMIC64
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select GENERIC_CLOCKEVENTS
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select GENERIC_FIND_FIRST_BIT
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# for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
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select GENERIC_IRQ_SHOW
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select GENERIC_PENDING_IRQ if SMP
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select GENERIC_SMP_IDLE_THREAD
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select HAVE_ARCH_KGDB
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select HAVE_ARCH_TRACEHOOK
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select HAVE_IOREMAP_PROT
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select HAVE_KPROBES
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select HAVE_KRETPROBES
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select HAVE_MEMBLOCK
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select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND
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select HAVE_OPROFILE
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select HAVE_PERF_EVENTS
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select IRQ_DOMAIN
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select MODULES_USE_ELF_RELA
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select NO_BOOTMEM
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select OF
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select OF_EARLY_FLATTREE
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select PERF_USE_VMALLOC
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select HAVE_DEBUG_STACKOVERFLOW
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config TRACE_IRQFLAGS_SUPPORT
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def_bool y
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config LOCKDEP_SUPPORT
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def_bool y
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config SCHED_OMIT_FRAME_POINTER
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def_bool y
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config GENERIC_CSUM
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def_bool y
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config RWSEM_GENERIC_SPINLOCK
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def_bool y
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config ARCH_FLATMEM_ENABLE
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def_bool y
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config MMU
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def_bool y
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config NO_IOPORT_MAP
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def_bool y
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config GENERIC_CALIBRATE_DELAY
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def_bool y
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config GENERIC_HWEIGHT
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def_bool y
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config STACKTRACE_SUPPORT
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def_bool y
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select STACKTRACE
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config HAVE_LATENCYTOP_SUPPORT
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def_bool y
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source "init/Kconfig"
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source "kernel/Kconfig.freezer"
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menu "ARC Architecture Configuration"
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menu "ARC Platform/SoC/Board"
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source "arch/arc/plat-sim/Kconfig"
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source "arch/arc/plat-tb10x/Kconfig"
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source "arch/arc/plat-axs10x/Kconfig"
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#New platform adds here
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endmenu
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choice
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prompt "ARC Instruction Set"
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default ISA_ARCOMPACT
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config ISA_ARCOMPACT
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bool "ARCompact ISA"
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help
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The original ARC ISA of ARC600/700 cores
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config ISA_ARCV2
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bool "ARC ISA v2"
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help
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ISA for the Next Generation ARC-HS cores
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endchoice
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menu "ARC CPU Configuration"
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choice
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prompt "ARC Core"
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default ARC_CPU_770 if ISA_ARCOMPACT
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default ARC_CPU_HS if ISA_ARCV2
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if ISA_ARCOMPACT
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config ARC_CPU_750D
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bool "ARC750D"
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select ARC_CANT_LLSC
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help
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Support for ARC750 core
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config ARC_CPU_770
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bool "ARC770"
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select ARC_HAS_SWAPE
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help
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Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
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This core has a bunch of cool new features:
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-MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
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Shared Address Spaces (for sharing TLB entires in MMU)
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-Caches: New Prog Model, Region Flush
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-Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
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endif #ISA_ARCOMPACT
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config ARC_CPU_HS
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bool "ARC-HS"
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depends on ISA_ARCV2
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help
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Support for ARC HS38x Cores based on ARCv2 ISA
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The notable features are:
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- SMP configurations of upto 4 core with coherency
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- Optional L2 Cache and IO-Coherency
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- Revised Interrupt Architecture (multiple priorites, reg banks,
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auto stack switch, auto regfile save/restore)
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- MMUv4 (PIPT dcache, Huge Pages)
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- Instructions for
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* 64bit load/store: LDD, STD
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* Hardware assisted divide/remainder: DIV, REM
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* Function prologue/epilogue: ENTER_S, LEAVE_S
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* IRQ enable/disable: CLRI, SETI
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* pop count: FFS, FLS
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* SETcc, BMSKN, XBFU...
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endchoice
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config CPU_BIG_ENDIAN
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bool "Enable Big Endian Mode"
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default n
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help
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Build kernel for Big Endian Mode of ARC CPU
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config SMP
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bool "Symmetric Multi-Processing"
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default n
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select ARC_HAS_COH_CACHES if ISA_ARCV2
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select ARC_MCIP if ISA_ARCV2
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help
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This enables support for systems with more than one CPU.
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if SMP
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config ARC_HAS_COH_CACHES
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def_bool n
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config ARC_HAS_REENTRANT_IRQ_LV2
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def_bool n
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config ARC_MCIP
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bool "ARConnect Multicore IP (MCIP) Support "
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depends on ISA_ARCV2
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help
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This IP block enables SMP in ARC-HS38 cores.
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It provides for cross-core interrupts, multi-core debug
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hardware semaphores, shared memory,....
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config NR_CPUS
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int "Maximum number of CPUs (2-4096)"
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range 2 4096
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default "4"
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endif #SMP
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menuconfig ARC_CACHE
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bool "Enable Cache Support"
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default y
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# if SMP, cache enabled ONLY if ARC implementation has cache coherency
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depends on !SMP || ARC_HAS_COH_CACHES
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if ARC_CACHE
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config ARC_CACHE_LINE_SHIFT
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int "Cache Line Length (as power of 2)"
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range 5 7
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default "6"
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help
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Starting with ARC700 4.9, Cache line length is configurable,
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This option specifies "N", with Line-len = 2 power N
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So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
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Linux only supports same line lengths for I and D caches.
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config ARC_HAS_ICACHE
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bool "Use Instruction Cache"
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default y
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config ARC_HAS_DCACHE
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bool "Use Data Cache"
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default y
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config ARC_CACHE_PAGES
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bool "Per Page Cache Control"
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default y
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depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
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help
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This can be used to over-ride the global I/D Cache Enable on a
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per-page basis (but only for pages accessed via MMU such as
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Kernel Virtual address or User Virtual Address)
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TLB entries have a per-page Cache Enable Bit.
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Note that Global I/D ENABLE + Per Page DISABLE works but corollary
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Global DISABLE + Per Page ENABLE won't work
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config ARC_CACHE_VIPT_ALIASING
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bool "Support VIPT Aliasing D$"
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depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
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default n
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endif #ARC_CACHE
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config ARC_HAS_ICCM
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bool "Use ICCM"
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help
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Single Cycle RAMS to store Fast Path Code
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default n
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config ARC_ICCM_SZ
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int "ICCM Size in KB"
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default "64"
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depends on ARC_HAS_ICCM
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config ARC_HAS_DCCM
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bool "Use DCCM"
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help
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Single Cycle RAMS to store Fast Path Data
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default n
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config ARC_DCCM_SZ
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int "DCCM Size in KB"
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default "64"
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depends on ARC_HAS_DCCM
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config ARC_DCCM_BASE
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hex "DCCM map address"
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default "0xA0000000"
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depends on ARC_HAS_DCCM
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config ARC_HAS_HW_MPY
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bool "Use Hardware Multiplier (Normal or Faster XMAC)"
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default y
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help
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Influences how gcc generates code for MPY operations.
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If enabled, MPYxx insns are generated, provided by Standard/XMAC
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Multipler. Otherwise software multipy lib is used
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choice
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prompt "MMU Version"
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default ARC_MMU_V3 if ARC_CPU_770
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default ARC_MMU_V2 if ARC_CPU_750D
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default ARC_MMU_V4 if ARC_CPU_HS
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config ARC_MMU_V1
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bool "MMU v1"
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help
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Orig ARC700 MMU
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config ARC_MMU_V2
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bool "MMU v2"
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help
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Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
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when 2 D-TLB and 1 I-TLB entries index into same 2way set.
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config ARC_MMU_V3
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bool "MMU v3"
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depends on ARC_CPU_770
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help
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Introduced with ARC700 4.10: New Features
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Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
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Shared Address Spaces (SASID)
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config ARC_MMU_V4
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bool "MMU v4"
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depends on ISA_ARCV2
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endchoice
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choice
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prompt "MMU Page Size"
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default ARC_PAGE_SIZE_8K
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config ARC_PAGE_SIZE_8K
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bool "8KB"
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help
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Choose between 8k vs 16k
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config ARC_PAGE_SIZE_16K
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bool "16KB"
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depends on ARC_MMU_V3 || ARC_MMU_V4
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config ARC_PAGE_SIZE_4K
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bool "4KB"
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depends on ARC_MMU_V3 || ARC_MMU_V4
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endchoice
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if ISA_ARCOMPACT
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config ARC_COMPACT_IRQ_LEVELS
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bool "ARCompact IRQ Priorities: High(2)/Low(1)"
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default n
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# Timer HAS to be high priority, for any other high priority config
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select ARC_IRQ3_LV2
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# if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
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depends on !SMP || ARC_HAS_REENTRANT_IRQ_LV2
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if ARC_COMPACT_IRQ_LEVELS
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config ARC_IRQ3_LV2
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bool
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config ARC_IRQ5_LV2
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bool
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config ARC_IRQ6_LV2
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bool
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endif #ARC_COMPACT_IRQ_LEVELS
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config ARC_FPU_SAVE_RESTORE
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bool "Enable FPU state persistence across context switch"
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default n
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help
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Double Precision Floating Point unit had dedictaed regs which
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need to be saved/restored across context-switch.
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Note that ARC FPU is overly simplistic, unlike say x86, which has
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hardware pieces to allow software to conditionally save/restore,
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based on actual usage of FPU by a task. Thus our implemn does
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this for all tasks in system.
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endif #ISA_ARCOMPACT
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config ARC_CANT_LLSC
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def_bool n
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config ARC_HAS_LLSC
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bool "Insn: LLOCK/SCOND (efficient atomic ops)"
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default y
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depends on !ARC_CANT_LLSC
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config ARC_STAR_9000923308
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bool "Workaround for llock/scond livelock"
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default y
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depends on ISA_ARCV2 && SMP && ARC_HAS_LLSC
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config ARC_HAS_SWAPE
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bool "Insn: SWAPE (endian-swap)"
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default y
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if ISA_ARCV2
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config ARC_HAS_LL64
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bool "Insn: 64bit LDD/STD"
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help
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Enable gcc to generate 64-bit load/store instructions
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ISA mandates even/odd registers to allow encoding of two
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dest operands with 2 possible source operands.
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default y
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config ARC_HAS_DIV_REM
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bool "Insn: div, divu, rem, remu"
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default y
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config ARC_HAS_RTC
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bool "Local 64-bit r/o cycle counter"
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default n
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depends on !SMP
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config ARC_HAS_GRTC
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bool "SMP synchronized 64-bit cycle counter"
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default y
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depends on SMP
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config ARC_NUMBER_OF_INTERRUPTS
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int "Number of interrupts"
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range 8 240
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default 32
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help
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This defines the number of interrupts on the ARCv2HS core.
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It affects the size of vector table.
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The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable
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in hardware, it keep things simple for Linux to assume they are always
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present.
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endif # ISA_ARCV2
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endmenu # "ARC CPU Configuration"
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config LINUX_LINK_BASE
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hex "Linux Link Address"
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default "0x80000000"
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help
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ARC700 divides the 32 bit phy address space into two equal halves
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-Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
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-Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
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Typically Linux kernel is linked at the start of untransalted addr,
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hence the default value of 0x8zs.
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However some customers have peripherals mapped at this addr, so
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Linux needs to be scooted a bit.
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If you don't know what the above means, leave this setting alone.
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config ARC_CURR_IN_REG
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bool "Dedicate Register r25 for current_task pointer"
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default y
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help
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This reserved Register R25 to point to Current Task in
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kernel mode. This saves memory access for each such access
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config ARC_EMUL_UNALIGNED
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bool "Emulate unaligned memory access (userspace only)"
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default N
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select SYSCTL_ARCH_UNALIGN_NO_WARN
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select SYSCTL_ARCH_UNALIGN_ALLOW
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depends on ISA_ARCOMPACT
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help
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This enables misaligned 16 & 32 bit memory access from user space.
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Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
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potential bugs in code
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config HZ
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int "Timer Frequency"
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default 100
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config ARC_METAWARE_HLINK
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bool "Support for Metaware debugger assisted Host access"
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default n
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help
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This options allows a Linux userland apps to directly access
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host file system (open/creat/read/write etc) with help from
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Metaware Debugger. This can come in handy for Linux-host communication
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when there is no real usable peripheral such as EMAC.
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menuconfig ARC_DBG
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bool "ARC debugging"
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default y
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if ARC_DBG
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config ARC_DW2_UNWIND
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bool "Enable DWARF specific kernel stack unwind"
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default y
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select KALLSYMS
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help
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Compiles the kernel with DWARF unwind information and can be used
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to get stack backtraces.
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If you say Y here the resulting kernel image will be slightly larger
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but not slower, and it will give very useful debugging information.
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If you don't debug the kernel, you can say N, but we may not be able
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to solve problems without frame unwind information
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config ARC_DBG_TLB_PARANOIA
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bool "Paranoia Checks in Low Level TLB Handlers"
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default n
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config ARC_DBG_TLB_MISS_COUNT
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bool "Profile TLB Misses"
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default n
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select DEBUG_FS
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help
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Counts number of I and D TLB Misses and exports them via Debugfs
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The counters can be cleared via Debugfs as well
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if SMP
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config ARC_IPI_DBG
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bool "Debug Inter Core interrupts"
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default n
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endif
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endif
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config ARC_UBOOT_SUPPORT
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bool "Support uboot arg Handling"
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default n
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help
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ARC Linux by default checks for uboot provided args as pointers to
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external cmdline or DTB. This however breaks in absence of uboot,
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when booting from Metaware debugger directly, as the registers are
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not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus
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registers look like uboot args to kernel which then chokes.
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So only enable the uboot arg checking/processing if users are sure
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of uboot being in play.
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config ARC_BUILTIN_DTB_NAME
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string "Built in DTB"
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help
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Set the name of the DTB to embed in the vmlinux binary
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Leaving it blank selects the minimal "skeleton" dtb
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source "kernel/Kconfig.preempt"
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menu "Executable file formats"
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source "fs/Kconfig.binfmt"
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endmenu
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endmenu # "ARC Architecture Configuration"
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source "mm/Kconfig"
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source "net/Kconfig"
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source "drivers/Kconfig"
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source "fs/Kconfig"
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source "arch/arc/Kconfig.debug"
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source "security/Kconfig"
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source "crypto/Kconfig"
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source "lib/Kconfig"
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source "kernel/power/Kconfig"
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