463 lines
12 KiB
C
463 lines
12 KiB
C
/*
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* pata_artop.c - ARTOP ATA controller driver
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*
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* (C) 2006 Red Hat
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* (C) 2007 Bartlomiej Zolnierkiewicz
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*
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* Based in part on drivers/ide/pci/aec62xx.c
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* Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
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* 865/865R fixes for Macintosh card version from a patch to the old
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* driver by Thibaut VARENE <varenet@parisc-linux.org>
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* When setting the PCI latency we must set 0x80 or higher for burst
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* performance Alessandro Zummo <alessandro.zummo@towertech.it>
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*
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* TODO
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* Investigate no_dsc on 850R
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* Clock detect
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#include <linux/ata.h>
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#define DRV_NAME "pata_artop"
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#define DRV_VERSION "0.4.5"
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/*
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* The ARTOP has 33 Mhz and "over clocked" timing tables. Until we
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* get PCI bus speed functionality we leave this as 0. Its a variable
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* for when we get the functionality and also for folks wanting to
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* test stuff.
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*/
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static int clock = 0;
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static int artop6210_pre_reset(struct ata_link *link, unsigned long deadline)
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{
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struct ata_port *ap = link->ap;
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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const struct pci_bits artop_enable_bits[] = {
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{ 0x4AU, 1U, 0x02UL, 0x02UL }, /* port 0 */
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{ 0x4AU, 1U, 0x04UL, 0x04UL }, /* port 1 */
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};
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if (!pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))
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return -ENOENT;
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return ata_sff_prereset(link, deadline);
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}
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/**
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* artop6260_pre_reset - check for 40/80 pin
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* @link: link
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* @deadline: deadline jiffies for the operation
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*
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* The ARTOP hardware reports the cable detect bits in register 0x49.
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* Nothing complicated needed here.
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*/
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static int artop6260_pre_reset(struct ata_link *link, unsigned long deadline)
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{
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static const struct pci_bits artop_enable_bits[] = {
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{ 0x4AU, 1U, 0x02UL, 0x02UL }, /* port 0 */
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{ 0x4AU, 1U, 0x04UL, 0x04UL }, /* port 1 */
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};
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struct ata_port *ap = link->ap;
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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/* Odd numbered device ids are the units with enable bits (the -R cards) */
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if (pdev->device % 1 && !pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))
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return -ENOENT;
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return ata_sff_prereset(link, deadline);
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}
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/**
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* artop6260_cable_detect - identify cable type
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* @ap: Port
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*
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* Identify the cable type for the ARTOP interface in question
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*/
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static int artop6260_cable_detect(struct ata_port *ap)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u8 tmp;
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pci_read_config_byte(pdev, 0x49, &tmp);
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if (tmp & (1 << ap->port_no))
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return ATA_CBL_PATA40;
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return ATA_CBL_PATA80;
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}
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/**
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* artop6210_load_piomode - Load a set of PATA PIO timings
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* @ap: Port whose timings we are configuring
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* @adev: Device
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* @pio: PIO mode
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*
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* Set PIO mode for device, in host controller PCI config space. This
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* is used both to set PIO timings in PIO mode and also to set the
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* matching PIO clocking for UDMA, as well as the MWDMA timings.
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*
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* LOCKING:
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* None (inherited from caller).
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*/
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static void artop6210_load_piomode(struct ata_port *ap, struct ata_device *adev, unsigned int pio)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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int dn = adev->devno + 2 * ap->port_no;
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const u16 timing[2][5] = {
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{ 0x0000, 0x000A, 0x0008, 0x0303, 0x0301 },
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{ 0x0700, 0x070A, 0x0708, 0x0403, 0x0401 }
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};
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/* Load the PIO timing active/recovery bits */
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pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]);
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}
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/**
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* artop6210_set_piomode - Initialize host controller PATA PIO timings
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* @ap: Port whose timings we are configuring
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* @adev: Device we are configuring
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*
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* Set PIO mode for device, in host controller PCI config space. For
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* ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
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* the event UDMA is used the later call to set_dmamode will set the
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* bits as required.
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*
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* LOCKING:
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* None (inherited from caller).
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*/
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static void artop6210_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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int dn = adev->devno + 2 * ap->port_no;
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u8 ultra;
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artop6210_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
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/* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
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pci_read_config_byte(pdev, 0x54, &ultra);
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ultra &= ~(3 << (2 * dn));
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pci_write_config_byte(pdev, 0x54, ultra);
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}
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/**
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* artop6260_load_piomode - Initialize host controller PATA PIO timings
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* @ap: Port whose timings we are configuring
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* @adev: Device we are configuring
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* @pio: PIO mode
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*
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* Set PIO mode for device, in host controller PCI config space. The
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* ARTOP6260 and relatives store the timing data differently.
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*
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* LOCKING:
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* None (inherited from caller).
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*/
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static void artop6260_load_piomode (struct ata_port *ap, struct ata_device *adev, unsigned int pio)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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int dn = adev->devno + 2 * ap->port_no;
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const u8 timing[2][5] = {
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{ 0x00, 0x0A, 0x08, 0x33, 0x31 },
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{ 0x70, 0x7A, 0x78, 0x43, 0x41 }
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};
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/* Load the PIO timing active/recovery bits */
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pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]);
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}
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/**
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* artop6260_set_piomode - Initialize host controller PATA PIO timings
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* @ap: Port whose timings we are configuring
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* @adev: Device we are configuring
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*
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* Set PIO mode for device, in host controller PCI config space. For
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* ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
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* the event UDMA is used the later call to set_dmamode will set the
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* bits as required.
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*
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* LOCKING:
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* None (inherited from caller).
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*/
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static void artop6260_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u8 ultra;
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artop6260_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
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/* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
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pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
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ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */
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pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
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}
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/**
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* artop6210_set_dmamode - Initialize host controller PATA PIO timings
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* @ap: Port whose timings we are configuring
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* @adev: Device whose timings we are configuring
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*
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* Set DMA mode for device, in host controller PCI config space.
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*
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* LOCKING:
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* None (inherited from caller).
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*/
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static void artop6210_set_dmamode (struct ata_port *ap, struct ata_device *adev)
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{
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unsigned int pio;
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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int dn = adev->devno + 2 * ap->port_no;
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u8 ultra;
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if (adev->dma_mode == XFER_MW_DMA_0)
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pio = 1;
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else
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pio = 4;
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/* Load the PIO timing active/recovery bits */
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artop6210_load_piomode(ap, adev, pio);
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pci_read_config_byte(pdev, 0x54, &ultra);
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ultra &= ~(3 << (2 * dn));
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/* Add ultra DMA bits if in UDMA mode */
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if (adev->dma_mode >= XFER_UDMA_0) {
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u8 mode = (adev->dma_mode - XFER_UDMA_0) + 1 - clock;
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if (mode == 0)
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mode = 1;
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ultra |= (mode << (2 * dn));
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}
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pci_write_config_byte(pdev, 0x54, ultra);
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}
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/**
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* artop6260_set_dmamode - Initialize host controller PATA PIO timings
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* @ap: Port whose timings we are configuring
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* @adev: Device we are configuring
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*
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* Set DMA mode for device, in host controller PCI config space. The
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* ARTOP6260 and relatives store the timing data differently.
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*
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* LOCKING:
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* None (inherited from caller).
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*/
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static void artop6260_set_dmamode (struct ata_port *ap, struct ata_device *adev)
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{
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unsigned int pio = adev->pio_mode - XFER_PIO_0;
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u8 ultra;
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if (adev->dma_mode == XFER_MW_DMA_0)
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pio = 1;
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else
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pio = 4;
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/* Load the PIO timing active/recovery bits */
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artop6260_load_piomode(ap, adev, pio);
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/* Add ultra DMA bits if in UDMA mode */
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pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
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ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */
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if (adev->dma_mode >= XFER_UDMA_0) {
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u8 mode = adev->dma_mode - XFER_UDMA_0 + 1 - clock;
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if (mode == 0)
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mode = 1;
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ultra |= (mode << (4 * adev->devno));
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}
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pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
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}
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/**
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* artop_6210_qc_defer - implement serialization
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* @qc: command
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*
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* Issue commands per host on this chip.
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*/
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static int artop6210_qc_defer(struct ata_queued_cmd *qc)
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{
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struct ata_host *host = qc->ap->host;
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struct ata_port *alt = host->ports[1 ^ qc->ap->port_no];
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int rc;
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/* First apply the usual rules */
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rc = ata_std_qc_defer(qc);
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if (rc != 0)
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return rc;
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/* Now apply serialization rules. Only allow a command if the
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other channel state machine is idle */
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if (alt && alt->qc_active)
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return ATA_DEFER_PORT;
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return 0;
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}
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static struct scsi_host_template artop_sht = {
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ATA_BMDMA_SHT(DRV_NAME),
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};
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static struct ata_port_operations artop6210_ops = {
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.inherits = &ata_bmdma_port_ops,
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.cable_detect = ata_cable_40wire,
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.set_piomode = artop6210_set_piomode,
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.set_dmamode = artop6210_set_dmamode,
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.prereset = artop6210_pre_reset,
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.qc_defer = artop6210_qc_defer,
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};
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static struct ata_port_operations artop6260_ops = {
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.inherits = &ata_bmdma_port_ops,
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.cable_detect = artop6260_cable_detect,
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.set_piomode = artop6260_set_piomode,
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.set_dmamode = artop6260_set_dmamode,
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.prereset = artop6260_pre_reset,
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};
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/**
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* artop_init_one - Register ARTOP ATA PCI device with kernel services
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* @pdev: PCI device to register
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* @ent: Entry in artop_pci_tbl matching with @pdev
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*
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* Called from kernel PCI layer.
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*
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* LOCKING:
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* Inherited from PCI layer (may sleep).
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*
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* RETURNS:
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* Zero on success, or -ERRNO value.
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*/
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static int artop_init_one (struct pci_dev *pdev, const struct pci_device_id *id)
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{
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static int printed_version;
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static const struct ata_port_info info_6210 = {
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.flags = ATA_FLAG_SLAVE_POSS,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA2,
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.port_ops = &artop6210_ops,
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};
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static const struct ata_port_info info_626x = {
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.flags = ATA_FLAG_SLAVE_POSS,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA4,
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.port_ops = &artop6260_ops,
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};
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static const struct ata_port_info info_628x = {
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.flags = ATA_FLAG_SLAVE_POSS,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA5,
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.port_ops = &artop6260_ops,
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};
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static const struct ata_port_info info_628x_fast = {
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.flags = ATA_FLAG_SLAVE_POSS,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA6,
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.port_ops = &artop6260_ops,
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};
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const struct ata_port_info *ppi[] = { NULL, NULL };
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int rc;
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if (!printed_version++)
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dev_printk(KERN_DEBUG, &pdev->dev,
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"version " DRV_VERSION "\n");
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rc = pcim_enable_device(pdev);
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if (rc)
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return rc;
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if (id->driver_data == 0) { /* 6210 variant */
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ppi[0] = &info_6210;
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/* BIOS may have left us in UDMA, clear it before libata probe */
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pci_write_config_byte(pdev, 0x54, 0);
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}
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else if (id->driver_data == 1) /* 6260 */
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ppi[0] = &info_626x;
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else if (id->driver_data == 2) { /* 6280 or 6280 + fast */
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unsigned long io = pci_resource_start(pdev, 4);
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u8 reg;
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ppi[0] = &info_628x;
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if (inb(io) & 0x10)
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ppi[0] = &info_628x_fast;
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/* Mac systems come up with some registers not set as we
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will need them */
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/* Clear reset & test bits */
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pci_read_config_byte(pdev, 0x49, ®);
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pci_write_config_byte(pdev, 0x49, reg & ~ 0x30);
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/* PCI latency must be > 0x80 for burst mode, tweak it
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* if required.
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*/
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pci_read_config_byte(pdev, PCI_LATENCY_TIMER, ®);
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if (reg <= 0x80)
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pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x90);
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/* Enable IRQ output and burst mode */
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pci_read_config_byte(pdev, 0x4a, ®);
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pci_write_config_byte(pdev, 0x4a, (reg & ~0x01) | 0x80);
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}
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BUG_ON(ppi[0] == NULL);
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return ata_pci_bmdma_init_one(pdev, ppi, &artop_sht, NULL, 0);
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}
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static const struct pci_device_id artop_pci_tbl[] = {
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{ PCI_VDEVICE(ARTOP, 0x0005), 0 },
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{ PCI_VDEVICE(ARTOP, 0x0006), 1 },
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{ PCI_VDEVICE(ARTOP, 0x0007), 1 },
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{ PCI_VDEVICE(ARTOP, 0x0008), 2 },
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{ PCI_VDEVICE(ARTOP, 0x0009), 2 },
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{ } /* terminate list */
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};
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static struct pci_driver artop_pci_driver = {
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.name = DRV_NAME,
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.id_table = artop_pci_tbl,
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.probe = artop_init_one,
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.remove = ata_pci_remove_one,
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};
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static int __init artop_init(void)
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{
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return pci_register_driver(&artop_pci_driver);
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}
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static void __exit artop_exit(void)
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{
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pci_unregister_driver(&artop_pci_driver);
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}
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module_init(artop_init);
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module_exit(artop_exit);
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MODULE_AUTHOR("Alan Cox");
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MODULE_DESCRIPTION("SCSI low-level driver for ARTOP PATA");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, artop_pci_tbl);
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MODULE_VERSION(DRV_VERSION);
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