129 lines
3.9 KiB
C
129 lines
3.9 KiB
C
/*
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* ARM64 cacheinfo support
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*
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* Copyright (C) 2015 ARM Ltd.
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/bitops.h>
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#include <linux/cacheinfo.h>
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#include <linux/cpu.h>
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#include <linux/compiler.h>
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#include <linux/of.h>
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#include <asm/cachetype.h>
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#include <asm/processor.h>
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#define MAX_CACHE_LEVEL 7 /* Max 7 level supported */
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/* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */
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#define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1))
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#define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level))
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#define CLIDR_CTYPE(clidr, level) \
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(((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))
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static inline enum cache_type get_cache_type(int level)
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{
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u64 clidr;
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if (level > MAX_CACHE_LEVEL)
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return CACHE_TYPE_NOCACHE;
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asm volatile ("mrs %x0, clidr_el1" : "=r" (clidr));
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return CLIDR_CTYPE(clidr, level);
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}
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/*
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* Cache Size Selection Register(CSSELR) selects which Cache Size ID
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* Register(CCSIDR) is accessible by specifying the required cache
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* level and the cache type. We need to ensure that no one else changes
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* CSSELR by calling this in non-preemtible context
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*/
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u64 __attribute_const__ cache_get_ccsidr(u64 csselr)
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{
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u64 ccsidr;
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WARN_ON(preemptible());
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/* Put value into CSSELR */
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asm volatile("msr csselr_el1, %x0" : : "r" (csselr));
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isb();
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/* Read result out of CCSIDR */
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asm volatile("mrs %x0, ccsidr_el1" : "=r" (ccsidr));
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return ccsidr;
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}
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static void ci_leaf_init(struct cacheinfo *this_leaf,
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enum cache_type type, unsigned int level)
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{
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bool is_icache = type & CACHE_TYPE_INST;
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u64 tmp = cache_get_ccsidr((level - 1) << 1 | is_icache);
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this_leaf->level = level;
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this_leaf->type = type;
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this_leaf->coherency_line_size = CACHE_LINESIZE(tmp);
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this_leaf->number_of_sets = CACHE_NUMSETS(tmp);
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this_leaf->ways_of_associativity = CACHE_ASSOCIATIVITY(tmp);
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this_leaf->size = this_leaf->number_of_sets *
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this_leaf->coherency_line_size * this_leaf->ways_of_associativity;
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this_leaf->attributes =
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((tmp & CCSIDR_EL1_WRITE_THROUGH) ? CACHE_WRITE_THROUGH : 0) |
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((tmp & CCSIDR_EL1_WRITE_BACK) ? CACHE_WRITE_BACK : 0) |
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((tmp & CCSIDR_EL1_READ_ALLOCATE) ? CACHE_READ_ALLOCATE : 0) |
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((tmp & CCSIDR_EL1_WRITE_ALLOCATE) ? CACHE_WRITE_ALLOCATE : 0);
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}
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static int __init_cache_level(unsigned int cpu)
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{
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unsigned int ctype, level, leaves;
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struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
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for (level = 1, leaves = 0; level <= MAX_CACHE_LEVEL; level++) {
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ctype = get_cache_type(level);
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if (ctype == CACHE_TYPE_NOCACHE) {
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level--;
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break;
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}
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/* Separate instruction and data caches */
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leaves += (ctype == CACHE_TYPE_SEPARATE) ? 2 : 1;
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}
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this_cpu_ci->num_levels = level;
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this_cpu_ci->num_leaves = leaves;
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return 0;
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}
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static int __populate_cache_leaves(unsigned int cpu)
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{
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unsigned int level, idx;
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enum cache_type type;
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struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
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struct cacheinfo *this_leaf = this_cpu_ci->info_list;
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for (idx = 0, level = 1; level <= this_cpu_ci->num_levels &&
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idx < this_cpu_ci->num_leaves; idx++, level++) {
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type = get_cache_type(level);
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if (type == CACHE_TYPE_SEPARATE) {
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ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
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ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
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} else {
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ci_leaf_init(this_leaf++, type, level);
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}
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}
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return 0;
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}
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DEFINE_SMP_CALL_CACHE_FUNCTION(init_cache_level)
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DEFINE_SMP_CALL_CACHE_FUNCTION(populate_cache_leaves)
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