306 lines
6.9 KiB
C
306 lines
6.9 KiB
C
/*
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* Copyright 2014 IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/pci.h>
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#include <misc/cxl.h>
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#include "cxl.h"
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static int cxl_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
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{
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if (dma_mask < DMA_BIT_MASK(64)) {
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pr_info("%s only 64bit DMA supported on CXL", __func__);
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return -EIO;
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}
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*(pdev->dev.dma_mask) = dma_mask;
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return 0;
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}
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static int cxl_pci_probe_mode(struct pci_bus *bus)
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{
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return PCI_PROBE_NORMAL;
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}
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static int cxl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
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{
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return -ENODEV;
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}
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static void cxl_teardown_msi_irqs(struct pci_dev *pdev)
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{
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/*
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* MSI should never be set but need still need to provide this call
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* back.
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*/
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}
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static bool cxl_pci_enable_device_hook(struct pci_dev *dev)
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{
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struct pci_controller *phb;
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struct cxl_afu *afu;
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struct cxl_context *ctx;
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phb = pci_bus_to_host(dev->bus);
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afu = (struct cxl_afu *)phb->private_data;
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set_dma_ops(&dev->dev, &dma_direct_ops);
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set_dma_offset(&dev->dev, PAGE_OFFSET);
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/*
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* Allocate a context to do cxl things too. If we eventually do real
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* DMA ops, we'll need a default context to attach them to
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*/
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ctx = cxl_dev_context_init(dev);
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if (!ctx)
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return false;
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dev->dev.archdata.cxl_ctx = ctx;
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return (cxl_afu_check_and_enable(afu) == 0);
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}
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static void cxl_pci_disable_device(struct pci_dev *dev)
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{
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struct cxl_context *ctx = cxl_get_context(dev);
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if (ctx) {
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if (ctx->status == STARTED) {
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dev_err(&dev->dev, "Default context started\n");
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return;
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}
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dev->dev.archdata.cxl_ctx = NULL;
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cxl_release_context(ctx);
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}
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}
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static resource_size_t cxl_pci_window_alignment(struct pci_bus *bus,
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unsigned long type)
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{
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return 1;
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}
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static void cxl_pci_reset_secondary_bus(struct pci_dev *dev)
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{
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/* Should we do an AFU reset here ? */
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}
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static int cxl_pcie_cfg_record(u8 bus, u8 devfn)
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{
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return (bus << 8) + devfn;
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}
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static unsigned long cxl_pcie_cfg_addr(struct pci_controller* phb,
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u8 bus, u8 devfn, int offset)
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{
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int record = cxl_pcie_cfg_record(bus, devfn);
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return (unsigned long)phb->cfg_addr + ((unsigned long)phb->cfg_data * record) + offset;
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}
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static int cxl_pcie_config_info(struct pci_bus *bus, unsigned int devfn,
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int offset, int len,
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volatile void __iomem **ioaddr,
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u32 *mask, int *shift)
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{
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struct pci_controller *phb;
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struct cxl_afu *afu;
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unsigned long addr;
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phb = pci_bus_to_host(bus);
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if (phb == NULL)
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return PCIBIOS_DEVICE_NOT_FOUND;
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afu = (struct cxl_afu *)phb->private_data;
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if (cxl_pcie_cfg_record(bus->number, devfn) > afu->crs_num)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (offset >= (unsigned long)phb->cfg_data)
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return PCIBIOS_BAD_REGISTER_NUMBER;
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addr = cxl_pcie_cfg_addr(phb, bus->number, devfn, offset);
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*ioaddr = (void *)(addr & ~0x3ULL);
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*shift = ((addr & 0x3) * 8);
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switch (len) {
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case 1:
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*mask = 0xff;
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break;
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case 2:
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*mask = 0xffff;
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break;
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default:
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*mask = 0xffffffff;
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break;
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}
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return 0;
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}
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static inline bool cxl_config_link_ok(struct pci_bus *bus)
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{
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struct pci_controller *phb;
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struct cxl_afu *afu;
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/* Config space IO is based on phb->cfg_addr, which is based on
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* afu_desc_mmio. This isn't safe to read/write when the link
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* goes down, as EEH tears down MMIO space.
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*
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* Check if the link is OK before proceeding.
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*/
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phb = pci_bus_to_host(bus);
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if (phb == NULL)
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return false;
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afu = (struct cxl_afu *)phb->private_data;
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return cxl_adapter_link_ok(afu->adapter);
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}
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static int cxl_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 *val)
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{
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volatile void __iomem *ioaddr;
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int shift, rc;
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u32 mask;
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rc = cxl_pcie_config_info(bus, devfn, offset, len, &ioaddr,
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&mask, &shift);
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if (rc)
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return rc;
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if (!cxl_config_link_ok(bus))
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return PCIBIOS_DEVICE_NOT_FOUND;
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/* Can only read 32 bits */
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*val = (in_le32(ioaddr) >> shift) & mask;
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return PCIBIOS_SUCCESSFUL;
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}
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static int cxl_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 val)
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{
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volatile void __iomem *ioaddr;
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u32 v, mask;
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int shift, rc;
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rc = cxl_pcie_config_info(bus, devfn, offset, len, &ioaddr,
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&mask, &shift);
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if (rc)
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return rc;
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if (!cxl_config_link_ok(bus))
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return PCIBIOS_DEVICE_NOT_FOUND;
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/* Can only write 32 bits so do read-modify-write */
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mask <<= shift;
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val <<= shift;
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v = (in_le32(ioaddr) & ~mask) || (val & mask);
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out_le32(ioaddr, v);
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops cxl_pcie_pci_ops =
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{
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.read = cxl_pcie_read_config,
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.write = cxl_pcie_write_config,
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};
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static struct pci_controller_ops cxl_pci_controller_ops =
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{
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.probe_mode = cxl_pci_probe_mode,
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.enable_device_hook = cxl_pci_enable_device_hook,
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.disable_device = cxl_pci_disable_device,
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.release_device = cxl_pci_disable_device,
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.window_alignment = cxl_pci_window_alignment,
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.reset_secondary_bus = cxl_pci_reset_secondary_bus,
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.setup_msi_irqs = cxl_setup_msi_irqs,
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.teardown_msi_irqs = cxl_teardown_msi_irqs,
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.dma_set_mask = cxl_dma_set_mask,
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};
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int cxl_pci_vphb_add(struct cxl_afu *afu)
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{
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struct pci_dev *phys_dev;
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struct pci_controller *phb, *phys_phb;
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phys_dev = to_pci_dev(afu->adapter->dev.parent);
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phys_phb = pci_bus_to_host(phys_dev->bus);
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/* Alloc and setup PHB data structure */
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phb = pcibios_alloc_controller(phys_phb->dn);
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if (!phb)
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return -ENODEV;
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/* Setup parent in sysfs */
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phb->parent = &phys_dev->dev;
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/* Setup the PHB using arch provided callback */
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phb->ops = &cxl_pcie_pci_ops;
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phb->cfg_addr = afu->afu_desc_mmio + afu->crs_offset;
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phb->cfg_data = (void *)(u64)afu->crs_len;
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phb->private_data = afu;
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phb->controller_ops = cxl_pci_controller_ops;
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/* Scan the bus */
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pcibios_scan_phb(phb);
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if (phb->bus == NULL)
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return -ENXIO;
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/* Claim resources. This might need some rework as well depending
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* whether we are doing probe-only or not, like assigning unassigned
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* resources etc...
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*/
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pcibios_claim_one_bus(phb->bus);
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/* Add probed PCI devices to the device model */
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pci_bus_add_devices(phb->bus);
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afu->phb = phb;
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return 0;
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}
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void cxl_pci_vphb_reconfigure(struct cxl_afu *afu)
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{
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/* When we are reconfigured, the AFU's MMIO space is unmapped
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* and remapped. We need to reflect this in the PHB's view of
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* the world.
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*/
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afu->phb->cfg_addr = afu->afu_desc_mmio + afu->crs_offset;
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}
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void cxl_pci_vphb_remove(struct cxl_afu *afu)
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{
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struct pci_controller *phb;
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/* If there is no configuration record we won't have one of these */
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if (!afu || !afu->phb)
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return;
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phb = afu->phb;
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pci_remove_root_bus(phb->bus);
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}
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struct cxl_afu *cxl_pci_to_afu(struct pci_dev *dev)
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{
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struct pci_controller *phb;
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phb = pci_bus_to_host(dev->bus);
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return (struct cxl_afu *)phb->private_data;
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}
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EXPORT_SYMBOL_GPL(cxl_pci_to_afu);
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unsigned int cxl_pci_to_cfg_record(struct pci_dev *dev)
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{
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return cxl_pcie_cfg_record(dev->bus->number, dev->devfn);
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}
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EXPORT_SYMBOL_GPL(cxl_pci_to_cfg_record);
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