479 lines
11 KiB
Plaintext
479 lines
11 KiB
Plaintext
/*
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* MPC8315E RDB Device Tree Source
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*
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* Copyright 2007 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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compatible = "fsl,mpc8315erdb";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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pci1 = &pci1;
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pci2 = &pci2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8315@0 {
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device_type = "cpu";
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reg = <0x0>;
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d-cache-line-size = <32>;
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i-cache-line-size = <32>;
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d-cache-size = <16384>;
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i-cache-size = <16384>;
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timebase-frequency = <0>; // from bootloader
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bus-frequency = <0>; // from bootloader
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clock-frequency = <0>; // from bootloader
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x08000000>; // 128MB at 0
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};
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localbus@e0005000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
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reg = <0xe0005000 0x1000>;
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interrupts = <77 0x8>;
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interrupt-parent = <&ipic>;
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// CS0 and CS1 are swapped when
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// booting from nand, but the
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// addresses are the same.
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ranges = <0x0 0x0 0xfe000000 0x00800000
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0x1 0x0 0xe0600000 0x00002000
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0x2 0x0 0xf0000000 0x00020000
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0x3 0x0 0xfa000000 0x00008000>;
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flash@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x800000>;
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bank-width = <2>;
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device-width = <1>;
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};
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nand@1,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8315-fcm-nand",
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"fsl,elbc-fcm-nand";
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reg = <0x1 0x0 0x2000>;
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u-boot@0 {
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reg = <0x0 0x100000>;
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read-only;
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};
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kernel@100000 {
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reg = <0x100000 0x300000>;
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};
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fs@400000 {
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reg = <0x400000 0x1c00000>;
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};
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};
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};
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immr@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "fsl,mpc8315-immr", "simple-bus";
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ranges = <0 0xe0000000 0x00100000>;
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reg = <0xe0000000 0x00000200>;
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bus-frequency = <0>;
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wdt@200 {
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device_type = "watchdog";
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compatible = "mpc83xx_wdt";
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reg = <0x200 0x100>;
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};
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <14 0x8>;
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interrupt-parent = <&ipic>;
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dfsrr;
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rtc@68 {
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compatible = "dallas,ds1339";
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reg = <0x68>;
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};
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mcu_pio: mcu@a {
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#gpio-cells = <2>;
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compatible = "fsl,mc9s08qg8-mpc8315erdb",
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"fsl,mcu-mpc8349emitx";
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reg = <0x0a>;
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gpio-controller;
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};
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};
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spi@7000 {
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cell-index = <0>;
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compatible = "fsl,spi";
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reg = <0x7000 0x1000>;
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interrupts = <16 0x8>;
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interrupt-parent = <&ipic>;
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mode = "cpu";
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};
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dma@82a8 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8315-dma", "fsl,elo-dma";
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reg = <0x82a8 4>;
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ranges = <0 0x8100 0x1a8>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
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reg = <0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
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reg = <0x180 0x28>;
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cell-index = <3>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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};
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usb@23000 {
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compatible = "fsl-usb2-dr";
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reg = <0x23000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&ipic>;
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interrupts = <38 0x8>;
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phy_type = "utmi";
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};
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enet0: ethernet@24000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <0>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x24000 0x1000>;
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ranges = <0x0 0x24000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <32 0x8 33 0x8 34 0x8>;
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interrupt-parent = <&ipic>;
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tbi-handle = <&tbi0>;
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phy-handle = < &phy0 >;
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fsl,magic-packet;
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-mdio";
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reg = <0x520 0x20>;
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phy0: ethernet-phy@0 {
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interrupt-parent = <&ipic>;
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interrupts = <20 0x8>;
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reg = <0x0>;
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};
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phy1: ethernet-phy@1 {
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interrupt-parent = <&ipic>;
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interrupts = <19 0x8>;
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reg = <0x1>;
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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enet1: ethernet@25000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <1>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x25000 0x1000>;
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ranges = <0x0 0x25000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <35 0x8 36 0x8 37 0x8>;
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interrupt-parent = <&ipic>;
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tbi-handle = <&tbi1>;
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phy-handle = < &phy1 >;
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fsl,magic-packet;
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-tbi";
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reg = <0x520 0x20>;
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tbi1: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "fsl,ns16550", "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <133333333>;
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interrupts = <9 0x8>;
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interrupt-parent = <&ipic>;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "fsl,ns16550", "ns16550";
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reg = <0x4600 0x100>;
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clock-frequency = <133333333>;
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interrupts = <10 0x8>;
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interrupt-parent = <&ipic>;
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};
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crypto@30000 {
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compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
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"fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
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"fsl,sec2.0";
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reg = <0x30000 0x10000>;
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interrupts = <11 0x8>;
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interrupt-parent = <&ipic>;
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fsl,num-channels = <4>;
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fsl,channel-fifo-len = <24>;
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fsl,exec-units-mask = <0x97c>;
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fsl,descriptor-types-mask = <0x3a30abf>;
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};
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sata@18000 {
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compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
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reg = <0x18000 0x1000>;
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cell-index = <1>;
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interrupts = <44 0x8>;
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interrupt-parent = <&ipic>;
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};
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sata@19000 {
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compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
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reg = <0x19000 0x1000>;
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cell-index = <2>;
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interrupts = <45 0x8>;
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interrupt-parent = <&ipic>;
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};
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gtm1: timer@500 {
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compatible = "fsl,mpc8315-gtm", "fsl,gtm";
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reg = <0x500 0x100>;
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interrupts = <90 8 78 8 84 8 72 8>;
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interrupt-parent = <&ipic>;
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clock-frequency = <133333333>;
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};
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timer@600 {
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compatible = "fsl,mpc8315-gtm", "fsl,gtm";
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reg = <0x600 0x100>;
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interrupts = <91 8 79 8 85 8 73 8>;
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interrupt-parent = <&ipic>;
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clock-frequency = <133333333>;
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};
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/* IPIC
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* interrupts cell = <intr #, sense>
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* sense values match linux IORESOURCE_IRQ_* defines:
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* sense == 8: Level, low assertion
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* sense == 2: Edge, high-to-low change
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*/
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ipic: interrupt-controller@700 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x700 0x100>;
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device_type = "ipic";
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};
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ipic-msi@7c0 {
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compatible = "fsl,ipic-msi";
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reg = <0x7c0 0x40>;
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msi-available-ranges = <0 0x100>;
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interrupts = <0x43 0x8
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0x4 0x8
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0x51 0x8
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0x52 0x8
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0x56 0x8
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0x57 0x8
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0x58 0x8
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0x59 0x8>;
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interrupt-parent = < &ipic >;
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};
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pmc: power@b00 {
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compatible = "fsl,mpc8315-pmc", "fsl,mpc8313-pmc",
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"fsl,mpc8349-pmc";
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reg = <0xb00 0x100 0xa00 0x100>;
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interrupts = <80 8>;
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interrupt-parent = <&ipic>;
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fsl,mpc8313-wakeup-timer = <>m1>;
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};
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};
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pci0: pci@e0008500 {
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x0E -mini PCI */
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0x7000 0x0 0x0 0x1 &ipic 18 0x8
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0x7000 0x0 0x0 0x2 &ipic 18 0x8
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0x7000 0x0 0x0 0x3 &ipic 18 0x8
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0x7000 0x0 0x0 0x4 &ipic 18 0x8
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/* IDSEL 0x0F -mini PCI */
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0x7800 0x0 0x0 0x1 &ipic 17 0x8
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0x7800 0x0 0x0 0x2 &ipic 17 0x8
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0x7800 0x0 0x0 0x3 &ipic 17 0x8
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0x7800 0x0 0x0 0x4 &ipic 17 0x8
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/* IDSEL 0x10 - PCI slot */
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0x8000 0x0 0x0 0x1 &ipic 48 0x8
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0x8000 0x0 0x0 0x2 &ipic 17 0x8
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0x8000 0x0 0x0 0x3 &ipic 48 0x8
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0x8000 0x0 0x0 0x4 &ipic 17 0x8>;
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interrupt-parent = <&ipic>;
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interrupts = <66 0x8>;
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bus-range = <0x0 0x0>;
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ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
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0x42000000 0 0x80000000 0x80000000 0 0x10000000
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0x01000000 0 0x00000000 0xe0300000 0 0x00100000>;
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clock-frequency = <66666666>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xe0008500 0x100 /* internal registers */
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0xe0008300 0x8>; /* config space access registers */
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compatible = "fsl,mpc8349-pci";
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device_type = "pci";
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};
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pci1: pcie@e0009000 {
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie";
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reg = <0xe0009000 0x00001000>;
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ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
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0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
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bus-range = <0 255>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <0 0 0 1 &ipic 1 8
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0 0 0 2 &ipic 1 8
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0 0 0 3 &ipic 1 8
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0 0 0 4 &ipic 1 8>;
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clock-frequency = <0>;
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pcie@0 {
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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reg = <0 0 0 0 0>;
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ranges = <0x02000000 0 0xa0000000
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0x02000000 0 0xa0000000
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0 0x10000000
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0x01000000 0 0x00000000
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0x01000000 0 0x00000000
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0 0x00800000>;
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};
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};
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pci2: pcie@e000a000 {
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie";
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reg = <0xe000a000 0x00001000>;
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ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x10000000
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0x01000000 0 0x00000000 0xd1000000 0 0x00800000>;
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bus-range = <0 255>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <0 0 0 1 &ipic 2 8
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0 0 0 2 &ipic 2 8
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0 0 0 3 &ipic 2 8
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0 0 0 4 &ipic 2 8>;
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clock-frequency = <0>;
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pcie@0 {
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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reg = <0 0 0 0 0>;
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ranges = <0x02000000 0 0xc0000000
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0x02000000 0 0xc0000000
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0 0x10000000
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0x01000000 0 0x00000000
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0x01000000 0 0x00000000
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0 0x00800000>;
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};
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};
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leds {
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compatible = "gpio-leds";
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pwr {
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gpios = <&mcu_pio 0 0>;
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default-state = "on";
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};
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hdd {
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gpios = <&mcu_pio 1 0>;
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linux,default-trigger = "disk-activity";
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};
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};
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};
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