354 lines
8.8 KiB
C
354 lines
8.8 KiB
C
/*
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* pata_sl82c105.c - SL82C105 PATA for new ATA layer
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* (C) 2005 Red Hat Inc
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* Alan Cox <alan@redhat.com>
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*
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* Based in part on linux/drivers/ide/pci/sl82c105.c
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* SL82C105/Winbond 553 IDE driver
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*
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* and in part on the documentation and errata sheet
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*
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*
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* Note: The controller like many controllers has shared timings for
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* PIO and DMA. We thus flip to the DMA timings in dma_start and flip back
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* in the dma_stop function. Thus we actually don't need a set_dmamode
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* method as the PIO method is always called and will set the right PIO
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* timing parameters.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "pata_sl82c105"
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#define DRV_VERSION "0.3.3"
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enum {
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/*
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* SL82C105 PCI config register 0x40 bits.
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*/
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CTRL_IDE_IRQB = (1 << 30),
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CTRL_IDE_IRQA = (1 << 28),
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CTRL_LEGIRQ = (1 << 11),
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CTRL_P1F16 = (1 << 5),
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CTRL_P1EN = (1 << 4),
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CTRL_P0F16 = (1 << 1),
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CTRL_P0EN = (1 << 0)
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};
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/**
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* sl82c105_pre_reset - probe begin
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* @link: ATA link
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* @deadline: deadline jiffies for the operation
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*
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* Set up cable type and use generic probe init
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*/
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static int sl82c105_pre_reset(struct ata_link *link, unsigned long deadline)
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{
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static const struct pci_bits sl82c105_enable_bits[] = {
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{ 0x40, 1, 0x01, 0x01 },
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{ 0x40, 1, 0x10, 0x10 }
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};
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struct ata_port *ap = link->ap;
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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if (ap->port_no && !pci_test_config_bits(pdev, &sl82c105_enable_bits[ap->port_no]))
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return -ENOENT;
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return ata_sff_prereset(link, deadline);
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}
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/**
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* sl82c105_configure_piomode - set chip PIO timing
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* @ap: ATA interface
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* @adev: ATA device
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* @pio: PIO mode
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*
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* Called to do the PIO mode setup. Our timing registers are shared
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* so a configure_dmamode call will undo any work we do here and vice
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* versa
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*/
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static void sl82c105_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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static u16 pio_timing[5] = {
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0x50D, 0x407, 0x304, 0x242, 0x240
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};
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u16 dummy;
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int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);
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pci_write_config_word(pdev, timing, pio_timing[pio]);
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/* Can we lose this oddity of the old driver */
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pci_read_config_word(pdev, timing, &dummy);
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}
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/**
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* sl82c105_set_piomode - set initial PIO mode data
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Called to do the PIO mode setup. Our timing registers are shared
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* but we want to set the PIO timing by default.
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*/
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static void sl82c105_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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sl82c105_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
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}
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/**
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* sl82c105_configure_dmamode - set DMA mode in chip
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Load DMA cycle times into the chip ready for a DMA transfer
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* to occur.
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*/
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static void sl82c105_configure_dmamode(struct ata_port *ap, struct ata_device *adev)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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static u16 dma_timing[3] = {
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0x707, 0x201, 0x200
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};
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u16 dummy;
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int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);
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int dma = adev->dma_mode - XFER_MW_DMA_0;
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pci_write_config_word(pdev, timing, dma_timing[dma]);
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/* Can we lose this oddity of the old driver */
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pci_read_config_word(pdev, timing, &dummy);
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}
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/**
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* sl82c105_reset_engine - Reset the DMA engine
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* @ap: ATA interface
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*
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* The sl82c105 has some serious problems with the DMA engine
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* when transfers don't run as expected or ATAPI is used. The
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* recommended fix is to reset the engine each use using a chip
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* test register.
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*/
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static void sl82c105_reset_engine(struct ata_port *ap)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u16 val;
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pci_read_config_word(pdev, 0x7E, &val);
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pci_write_config_word(pdev, 0x7E, val | 4);
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pci_write_config_word(pdev, 0x7E, val & ~4);
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}
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/**
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* sl82c105_bmdma_start - DMA engine begin
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* @qc: ATA command
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*
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* Reset the DMA engine each use as recommended by the errata
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* document.
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*
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* FIXME: if we switch clock at BMDMA start/end we might get better
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* PIO performance on DMA capable devices.
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*/
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static void sl82c105_bmdma_start(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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udelay(100);
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sl82c105_reset_engine(ap);
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udelay(100);
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/* Set the clocks for DMA */
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sl82c105_configure_dmamode(ap, qc->dev);
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/* Activate DMA */
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ata_bmdma_start(qc);
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}
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/**
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* sl82c105_bmdma_end - DMA engine stop
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* @qc: ATA command
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*
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* Reset the DMA engine each use as recommended by the errata
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* document.
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*
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* This function is also called to turn off DMA when a timeout occurs
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* during DMA operation. In both cases we need to reset the engine,
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* so no actual eng_timeout handler is required.
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*
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* We assume bmdma_stop is always called if bmdma_start as called. If
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* not then we may need to wrap qc_issue.
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*/
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static void sl82c105_bmdma_stop(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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ata_bmdma_stop(qc);
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sl82c105_reset_engine(ap);
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udelay(100);
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/* This will redo the initial setup of the DMA device to matching
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PIO timings */
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sl82c105_set_piomode(ap, qc->dev);
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}
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/**
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* sl82c105_qc_defer - implement serialization
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* @qc: command
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*
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* We must issue one command per host not per channel because
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* of the reset bug.
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*
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* Q: is the scsi host lock sufficient ?
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*/
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static int sl82c105_qc_defer(struct ata_queued_cmd *qc)
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{
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struct ata_host *host = qc->ap->host;
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struct ata_port *alt = host->ports[1 ^ qc->ap->port_no];
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int rc;
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/* First apply the usual rules */
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rc = ata_std_qc_defer(qc);
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if (rc != 0)
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return rc;
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/* Now apply serialization rules. Only allow a command if the
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other channel state machine is idle */
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if (alt && alt->qc_active)
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return ATA_DEFER_PORT;
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return 0;
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}
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static struct scsi_host_template sl82c105_sht = {
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ATA_BMDMA_SHT(DRV_NAME),
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};
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static struct ata_port_operations sl82c105_port_ops = {
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.inherits = &ata_bmdma_port_ops,
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.qc_defer = sl82c105_qc_defer,
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.bmdma_start = sl82c105_bmdma_start,
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.bmdma_stop = sl82c105_bmdma_stop,
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.cable_detect = ata_cable_40wire,
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.set_piomode = sl82c105_set_piomode,
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.prereset = sl82c105_pre_reset,
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};
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/**
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* sl82c105_bridge_revision - find bridge version
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* @pdev: PCI device for the ATA function
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*
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* Locates the PCI bridge associated with the ATA function and
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* providing it is a Winbond 553 reports the revision. If it cannot
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* find a revision or the right device it returns -1
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*/
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static int sl82c105_bridge_revision(struct pci_dev *pdev)
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{
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struct pci_dev *bridge;
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/*
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* The bridge should be part of the same device, but function 0.
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*/
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bridge = pci_get_slot(pdev->bus,
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PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
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if (!bridge)
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return -1;
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/*
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* Make sure it is a Winbond 553 and is an ISA bridge.
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*/
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if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
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bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
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bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) {
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pci_dev_put(bridge);
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return -1;
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}
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/*
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* We need to find function 0's revision, not function 1
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*/
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pci_dev_put(bridge);
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return bridge->revision;
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}
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static int sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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static const struct ata_port_info info_dma = {
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.flags = ATA_FLAG_SLAVE_POSS,
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.pio_mask = 0x1f,
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.mwdma_mask = 0x07,
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.port_ops = &sl82c105_port_ops
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};
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static const struct ata_port_info info_early = {
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.flags = ATA_FLAG_SLAVE_POSS,
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.pio_mask = 0x1f,
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.port_ops = &sl82c105_port_ops
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};
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/* for now use only the first port */
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const struct ata_port_info *ppi[] = { &info_early,
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NULL };
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u32 val;
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int rev;
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int rc;
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rc = pcim_enable_device(dev);
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if (rc)
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return rc;
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rev = sl82c105_bridge_revision(dev);
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if (rev == -1)
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dev_printk(KERN_WARNING, &dev->dev, "pata_sl82c105: Unable to find bridge, disabling DMA.\n");
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else if (rev <= 5)
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dev_printk(KERN_WARNING, &dev->dev, "pata_sl82c105: Early bridge revision, no DMA available.\n");
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else
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ppi[0] = &info_dma;
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pci_read_config_dword(dev, 0x40, &val);
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val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
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pci_write_config_dword(dev, 0x40, val);
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return ata_pci_sff_init_one(dev, ppi, &sl82c105_sht, NULL);
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}
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static const struct pci_device_id sl82c105[] = {
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{ PCI_VDEVICE(WINBOND, PCI_DEVICE_ID_WINBOND_82C105), },
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{ },
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};
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static struct pci_driver sl82c105_pci_driver = {
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.name = DRV_NAME,
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.id_table = sl82c105,
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.probe = sl82c105_init_one,
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.remove = ata_pci_remove_one
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};
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static int __init sl82c105_init(void)
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{
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return pci_register_driver(&sl82c105_pci_driver);
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}
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static void __exit sl82c105_exit(void)
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{
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pci_unregister_driver(&sl82c105_pci_driver);
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}
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MODULE_AUTHOR("Alan Cox");
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MODULE_DESCRIPTION("low-level driver for Sl82c105");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, sl82c105);
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MODULE_VERSION(DRV_VERSION);
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module_init(sl82c105_init);
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module_exit(sl82c105_exit);
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