447 lines
10 KiB
C
447 lines
10 KiB
C
/*
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* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/clk/at91_pmc.h>
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#include <linux/of.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include "pmc.h"
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DEFINE_SPINLOCK(pmc_pcr_lock);
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#define PERIPHERAL_MAX 64
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#define PERIPHERAL_AT91RM9200 0
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#define PERIPHERAL_AT91SAM9X5 1
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#define PERIPHERAL_ID_MIN 2
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#define PERIPHERAL_ID_MAX 31
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#define PERIPHERAL_MASK(id) (1 << ((id) & PERIPHERAL_ID_MAX))
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#define PERIPHERAL_RSHIFT_MASK 0x3
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#define PERIPHERAL_RSHIFT(val) (((val) >> 16) & PERIPHERAL_RSHIFT_MASK)
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#define PERIPHERAL_MAX_SHIFT 3
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struct clk_peripheral {
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struct clk_hw hw;
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struct regmap *regmap;
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u32 id;
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};
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#define to_clk_peripheral(hw) container_of(hw, struct clk_peripheral, hw)
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struct clk_sam9x5_peripheral {
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struct clk_hw hw;
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struct regmap *regmap;
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struct clk_range range;
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spinlock_t *lock;
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u32 id;
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u32 div;
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bool auto_div;
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};
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#define to_clk_sam9x5_peripheral(hw) \
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container_of(hw, struct clk_sam9x5_peripheral, hw)
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static int clk_peripheral_enable(struct clk_hw *hw)
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{
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struct clk_peripheral *periph = to_clk_peripheral(hw);
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int offset = AT91_PMC_PCER;
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u32 id = periph->id;
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if (id < PERIPHERAL_ID_MIN)
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return 0;
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if (id > PERIPHERAL_ID_MAX)
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offset = AT91_PMC_PCER1;
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regmap_write(periph->regmap, offset, PERIPHERAL_MASK(id));
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return 0;
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}
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static void clk_peripheral_disable(struct clk_hw *hw)
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{
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struct clk_peripheral *periph = to_clk_peripheral(hw);
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int offset = AT91_PMC_PCDR;
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u32 id = periph->id;
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if (id < PERIPHERAL_ID_MIN)
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return;
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if (id > PERIPHERAL_ID_MAX)
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offset = AT91_PMC_PCDR1;
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regmap_write(periph->regmap, offset, PERIPHERAL_MASK(id));
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}
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static int clk_peripheral_is_enabled(struct clk_hw *hw)
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{
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struct clk_peripheral *periph = to_clk_peripheral(hw);
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int offset = AT91_PMC_PCSR;
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unsigned int status;
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u32 id = periph->id;
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if (id < PERIPHERAL_ID_MIN)
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return 1;
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if (id > PERIPHERAL_ID_MAX)
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offset = AT91_PMC_PCSR1;
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regmap_read(periph->regmap, offset, &status);
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return status & PERIPHERAL_MASK(id) ? 1 : 0;
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}
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static const struct clk_ops peripheral_ops = {
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.enable = clk_peripheral_enable,
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.disable = clk_peripheral_disable,
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.is_enabled = clk_peripheral_is_enabled,
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};
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static struct clk_hw * __init
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at91_clk_register_peripheral(struct regmap *regmap, const char *name,
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const char *parent_name, u32 id)
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{
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struct clk_peripheral *periph;
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struct clk_init_data init;
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struct clk_hw *hw;
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int ret;
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if (!name || !parent_name || id > PERIPHERAL_ID_MAX)
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return ERR_PTR(-EINVAL);
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periph = kzalloc(sizeof(*periph), GFP_KERNEL);
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if (!periph)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &peripheral_ops;
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init.parent_names = (parent_name ? &parent_name : NULL);
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init.num_parents = (parent_name ? 1 : 0);
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init.flags = 0;
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periph->id = id;
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periph->hw.init = &init;
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periph->regmap = regmap;
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hw = &periph->hw;
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ret = clk_hw_register(NULL, &periph->hw);
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if (ret) {
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kfree(periph);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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static void clk_sam9x5_peripheral_autodiv(struct clk_sam9x5_peripheral *periph)
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{
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struct clk_hw *parent;
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unsigned long parent_rate;
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int shift = 0;
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if (!periph->auto_div)
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return;
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if (periph->range.max) {
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parent = clk_hw_get_parent_by_index(&periph->hw, 0);
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parent_rate = clk_hw_get_rate(parent);
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if (!parent_rate)
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return;
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for (; shift < PERIPHERAL_MAX_SHIFT; shift++) {
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if (parent_rate >> shift <= periph->range.max)
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break;
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}
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}
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periph->auto_div = false;
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periph->div = shift;
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}
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static int clk_sam9x5_peripheral_enable(struct clk_hw *hw)
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{
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struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
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unsigned long flags;
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if (periph->id < PERIPHERAL_ID_MIN)
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return 0;
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spin_lock_irqsave(periph->lock, flags);
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regmap_write(periph->regmap, AT91_PMC_PCR,
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(periph->id & AT91_PMC_PCR_PID_MASK));
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regmap_update_bits(periph->regmap, AT91_PMC_PCR,
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AT91_PMC_PCR_DIV_MASK | AT91_PMC_PCR_CMD |
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AT91_PMC_PCR_EN,
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AT91_PMC_PCR_DIV(periph->div) |
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AT91_PMC_PCR_CMD |
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AT91_PMC_PCR_EN);
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spin_unlock_irqrestore(periph->lock, flags);
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return 0;
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}
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static void clk_sam9x5_peripheral_disable(struct clk_hw *hw)
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{
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struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
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unsigned long flags;
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if (periph->id < PERIPHERAL_ID_MIN)
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return;
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spin_lock_irqsave(periph->lock, flags);
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regmap_write(periph->regmap, AT91_PMC_PCR,
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(periph->id & AT91_PMC_PCR_PID_MASK));
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regmap_update_bits(periph->regmap, AT91_PMC_PCR,
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AT91_PMC_PCR_EN | AT91_PMC_PCR_CMD,
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AT91_PMC_PCR_CMD);
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spin_unlock_irqrestore(periph->lock, flags);
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}
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static int clk_sam9x5_peripheral_is_enabled(struct clk_hw *hw)
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{
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struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
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unsigned long flags;
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unsigned int status;
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if (periph->id < PERIPHERAL_ID_MIN)
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return 1;
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spin_lock_irqsave(periph->lock, flags);
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regmap_write(periph->regmap, AT91_PMC_PCR,
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(periph->id & AT91_PMC_PCR_PID_MASK));
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regmap_read(periph->regmap, AT91_PMC_PCR, &status);
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spin_unlock_irqrestore(periph->lock, flags);
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return status & AT91_PMC_PCR_EN ? 1 : 0;
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}
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static unsigned long
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clk_sam9x5_peripheral_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
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unsigned long flags;
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unsigned int status;
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if (periph->id < PERIPHERAL_ID_MIN)
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return parent_rate;
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spin_lock_irqsave(periph->lock, flags);
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regmap_write(periph->regmap, AT91_PMC_PCR,
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(periph->id & AT91_PMC_PCR_PID_MASK));
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regmap_read(periph->regmap, AT91_PMC_PCR, &status);
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spin_unlock_irqrestore(periph->lock, flags);
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if (status & AT91_PMC_PCR_EN) {
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periph->div = PERIPHERAL_RSHIFT(status);
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periph->auto_div = false;
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} else {
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clk_sam9x5_peripheral_autodiv(periph);
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}
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return parent_rate >> periph->div;
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}
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static long clk_sam9x5_peripheral_round_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long *parent_rate)
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{
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int shift = 0;
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unsigned long best_rate;
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unsigned long best_diff;
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unsigned long cur_rate = *parent_rate;
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unsigned long cur_diff;
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struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
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if (periph->id < PERIPHERAL_ID_MIN || !periph->range.max)
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return *parent_rate;
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if (periph->range.max) {
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for (; shift <= PERIPHERAL_MAX_SHIFT; shift++) {
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cur_rate = *parent_rate >> shift;
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if (cur_rate <= periph->range.max)
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break;
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}
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}
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if (rate >= cur_rate)
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return cur_rate;
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best_diff = cur_rate - rate;
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best_rate = cur_rate;
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for (; shift <= PERIPHERAL_MAX_SHIFT; shift++) {
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cur_rate = *parent_rate >> shift;
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if (cur_rate < rate)
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cur_diff = rate - cur_rate;
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else
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cur_diff = cur_rate - rate;
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if (cur_diff < best_diff) {
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best_diff = cur_diff;
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best_rate = cur_rate;
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}
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if (!best_diff || cur_rate < rate)
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break;
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}
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return best_rate;
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}
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static int clk_sam9x5_peripheral_set_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long parent_rate)
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{
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int shift;
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struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
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if (periph->id < PERIPHERAL_ID_MIN || !periph->range.max) {
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if (parent_rate == rate)
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return 0;
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else
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return -EINVAL;
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}
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if (periph->range.max && rate > periph->range.max)
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return -EINVAL;
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for (shift = 0; shift <= PERIPHERAL_MAX_SHIFT; shift++) {
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if (parent_rate >> shift == rate) {
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periph->auto_div = false;
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periph->div = shift;
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return 0;
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}
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}
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return -EINVAL;
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}
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static const struct clk_ops sam9x5_peripheral_ops = {
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.enable = clk_sam9x5_peripheral_enable,
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.disable = clk_sam9x5_peripheral_disable,
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.is_enabled = clk_sam9x5_peripheral_is_enabled,
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.recalc_rate = clk_sam9x5_peripheral_recalc_rate,
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.round_rate = clk_sam9x5_peripheral_round_rate,
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.set_rate = clk_sam9x5_peripheral_set_rate,
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};
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static struct clk_hw * __init
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at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *lock,
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const char *name, const char *parent_name,
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u32 id, const struct clk_range *range)
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{
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struct clk_sam9x5_peripheral *periph;
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struct clk_init_data init;
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struct clk_hw *hw;
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int ret;
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if (!name || !parent_name)
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return ERR_PTR(-EINVAL);
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periph = kzalloc(sizeof(*periph), GFP_KERNEL);
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if (!periph)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &sam9x5_peripheral_ops;
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init.parent_names = (parent_name ? &parent_name : NULL);
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init.num_parents = (parent_name ? 1 : 0);
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init.flags = 0;
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periph->id = id;
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periph->hw.init = &init;
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periph->div = 0;
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periph->regmap = regmap;
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periph->lock = lock;
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periph->auto_div = true;
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periph->range = *range;
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hw = &periph->hw;
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ret = clk_hw_register(NULL, &periph->hw);
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if (ret) {
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kfree(periph);
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hw = ERR_PTR(ret);
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} else
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clk_sam9x5_peripheral_autodiv(periph);
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return hw;
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}
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static void __init
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of_at91_clk_periph_setup(struct device_node *np, u8 type)
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{
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int num;
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u32 id;
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struct clk_hw *hw;
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const char *parent_name;
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const char *name;
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struct device_node *periphclknp;
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struct regmap *regmap;
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parent_name = of_clk_get_parent_name(np, 0);
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if (!parent_name)
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return;
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num = of_get_child_count(np);
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if (!num || num > PERIPHERAL_MAX)
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return;
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regmap = syscon_node_to_regmap(of_get_parent(np));
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if (IS_ERR(regmap))
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return;
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for_each_child_of_node(np, periphclknp) {
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if (of_property_read_u32(periphclknp, "reg", &id))
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continue;
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if (id >= PERIPHERAL_MAX)
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continue;
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if (of_property_read_string(np, "clock-output-names", &name))
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name = periphclknp->name;
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if (type == PERIPHERAL_AT91RM9200) {
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hw = at91_clk_register_peripheral(regmap, name,
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parent_name, id);
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} else {
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struct clk_range range = CLK_RANGE(0, 0);
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of_at91_get_clk_range(periphclknp,
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"atmel,clk-output-range",
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&range);
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hw = at91_clk_register_sam9x5_peripheral(regmap,
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&pmc_pcr_lock,
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name,
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parent_name,
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id, &range);
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}
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if (IS_ERR(hw))
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continue;
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of_clk_add_hw_provider(periphclknp, of_clk_hw_simple_get, hw);
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}
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}
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static void __init of_at91rm9200_clk_periph_setup(struct device_node *np)
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{
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of_at91_clk_periph_setup(np, PERIPHERAL_AT91RM9200);
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}
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CLK_OF_DECLARE(at91rm9200_clk_periph, "atmel,at91rm9200-clk-peripheral",
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of_at91rm9200_clk_periph_setup);
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static void __init of_at91sam9x5_clk_periph_setup(struct device_node *np)
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{
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of_at91_clk_periph_setup(np, PERIPHERAL_AT91SAM9X5);
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}
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CLK_OF_DECLARE(at91sam9x5_clk_periph, "atmel,at91sam9x5-clk-peripheral",
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of_at91sam9x5_clk_periph_setup);
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