212 lines
6.8 KiB
C
212 lines
6.8 KiB
C
/*
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* linux/arch/unicore32/include/asm/cacheflush.h
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*
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* Code specific to PKUnity SoC and UniCore ISA
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*
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* Copyright (C) 2001-2010 GUAN Xue-tao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __UNICORE_CACHEFLUSH_H__
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#define __UNICORE_CACHEFLUSH_H__
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#include <linux/mm.h>
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#include <asm/shmparam.h>
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#define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
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/*
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* This flag is used to indicate that the page pointed to by a pte is clean
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* and does not require cleaning before returning it to the user.
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*/
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#define PG_dcache_clean PG_arch_1
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/*
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* MM Cache Management
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* ===================
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*
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* The arch/unicore32/mm/cache.S files implement these methods.
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*
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* Start addresses are inclusive and end addresses are exclusive;
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* start addresses should be rounded down, end addresses up.
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*
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* See Documentation/cachetlb.txt for more information.
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* Please note that the implementation of these, and the required
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* effects are cache-type (VIVT/VIPT/PIPT) specific.
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*
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* flush_icache_all()
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*
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* Unconditionally clean and invalidate the entire icache.
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* Currently only needed for cache-v6.S and cache-v7.S, see
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* __flush_icache_all for the generic implementation.
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*
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* flush_kern_all()
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*
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* Unconditionally clean and invalidate the entire cache.
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*
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* flush_user_all()
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*
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* Clean and invalidate all user space cache entries
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* before a change of page tables.
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*
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* flush_user_range(start, end, flags)
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*
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* Clean and invalidate a range of cache entries in the
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* specified address space before a change of page tables.
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* - start - user start address (inclusive, page aligned)
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* - end - user end address (exclusive, page aligned)
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* - flags - vma->vm_flags field
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*
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* coherent_kern_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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* - start - virtual start address
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* - end - virtual end address
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*
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* coherent_user_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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* - start - virtual start address
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* - end - virtual end address
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*
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* flush_kern_dcache_area(kaddr, size)
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*
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* Ensure that the data held in page is written back.
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* - kaddr - page address
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* - size - region size
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*
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* DMA Cache Coherency
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* ===================
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*
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* dma_flush_range(start, end)
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*
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* Clean and invalidate the specified virtual address range.
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* - start - virtual start address
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* - end - virtual end address
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*/
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extern void __cpuc_flush_icache_all(void);
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extern void __cpuc_flush_kern_all(void);
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extern void __cpuc_flush_user_all(void);
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extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
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extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
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extern void __cpuc_coherent_user_range(unsigned long, unsigned long);
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extern void __cpuc_flush_dcache_area(void *, size_t);
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extern void __cpuc_flush_kern_dcache_area(void *addr, size_t size);
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/*
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* These are private to the dma-mapping API. Do not use directly.
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* Their sole purpose is to ensure that data held in the cache
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* is visible to DMA, or data written by DMA to system memory is
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* visible to the CPU.
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*/
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extern void __cpuc_dma_clean_range(unsigned long, unsigned long);
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extern void __cpuc_dma_flush_range(unsigned long, unsigned long);
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/*
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* Copy user data from/to a page which is mapped into a different
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* processes address space. Really, we want to allow our "user
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* space" model to handle this.
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*/
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extern void copy_to_user_page(struct vm_area_struct *, struct page *,
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unsigned long, void *, const void *, unsigned long);
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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memcpy(dst, src, len); \
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} while (0)
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/*
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* Convert calls to our calling convention.
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*/
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/* Invalidate I-cache */
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static inline void __flush_icache_all(void)
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{
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asm("movc p0.c5, %0, #20;\n"
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"nop; nop; nop; nop; nop; nop; nop; nop\n"
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:
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: "r" (0));
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}
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#define flush_cache_all() __cpuc_flush_kern_all()
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extern void flush_cache_mm(struct mm_struct *mm);
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extern void flush_cache_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end);
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extern void flush_cache_page(struct vm_area_struct *vma,
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unsigned long user_addr, unsigned long pfn);
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#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
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/*
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* flush_cache_user_range is used when we want to ensure that the
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* Harvard caches are synchronised for the user space address range.
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* This is used for the UniCore private sys_cacheflush system call.
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*/
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#define flush_cache_user_range(vma, start, end) \
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__cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
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/*
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* Perform necessary cache operations to ensure that data previously
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* stored within this range of addresses can be executed by the CPU.
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*/
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#define flush_icache_range(s, e) __cpuc_coherent_kern_range(s, e)
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/*
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* Perform necessary cache operations to ensure that the TLB will
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* see data written in the specified area.
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*/
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#define clean_dcache_area(start, size) cpu_dcache_clean_area(start, size)
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/*
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* flush_dcache_page is used when the kernel has written to the page
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* cache page at virtual address page->virtual.
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*
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* If this page isn't mapped (ie, page_mapping == NULL), or it might
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* have userspace mappings, then we _must_ always clean + invalidate
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* the dcache entries associated with the kernel mapping.
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*
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* Otherwise we can defer the operation, and clean the cache when we are
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* about to change to user space. This is the same method as used on SPARC64.
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* See update_mmu_cache for the user space part.
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*/
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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extern void flush_dcache_page(struct page *);
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#define flush_dcache_mmap_lock(mapping) \
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spin_lock_irq(&(mapping)->tree_lock)
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#define flush_dcache_mmap_unlock(mapping) \
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spin_unlock_irq(&(mapping)->tree_lock)
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#define flush_icache_user_range(vma, page, addr, len) \
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flush_dcache_page(page)
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/*
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* We don't appear to need to do anything here. In fact, if we did, we'd
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* duplicate cache flushing elsewhere performed by flush_dcache_page().
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*/
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#define flush_icache_page(vma, page) do { } while (0)
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/*
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* flush_cache_vmap() is used when creating mappings (eg, via vmap,
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* vmalloc, ioremap etc) in kernel space for pages. On non-VIPT
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* caches, since the direct-mappings of these pages may contain cached
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* data, we need to do a full cache flush to ensure that writebacks
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* don't corrupt data placed into these pages via the new mappings.
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*/
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static inline void flush_cache_vmap(unsigned long start, unsigned long end)
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{
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}
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static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
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{
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}
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#endif
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