331 lines
8.2 KiB
C
331 lines
8.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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//
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// Copyright (c) 2013-2014 Freescale Semiconductor, Inc
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// Copyright (c) 2017 Sysam, Angelo Dureghello <angelo@sysam.it>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/dmaengine.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/dma-mcf-edma.h>
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#include "fsl-edma-common.h"
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#define EDMA_CHANNELS 64
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#define EDMA_MASK_CH(x) ((x) & GENMASK(5, 0))
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static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id)
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{
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struct fsl_edma_engine *mcf_edma = dev_id;
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struct edma_regs *regs = &mcf_edma->regs;
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unsigned int ch;
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struct fsl_edma_chan *mcf_chan;
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u64 intmap;
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intmap = ioread32(regs->inth);
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intmap <<= 32;
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intmap |= ioread32(regs->intl);
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if (!intmap)
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return IRQ_NONE;
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for (ch = 0; ch < mcf_edma->n_chans; ch++) {
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if (intmap & BIT(ch)) {
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iowrite8(EDMA_MASK_CH(ch), regs->cint);
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mcf_chan = &mcf_edma->chans[ch];
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spin_lock(&mcf_chan->vchan.lock);
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if (!mcf_chan->edesc) {
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/* terminate_all called before */
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spin_unlock(&mcf_chan->vchan.lock);
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continue;
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}
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if (!mcf_chan->edesc->iscyclic) {
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list_del(&mcf_chan->edesc->vdesc.node);
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vchan_cookie_complete(&mcf_chan->edesc->vdesc);
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mcf_chan->edesc = NULL;
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mcf_chan->status = DMA_COMPLETE;
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mcf_chan->idle = true;
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} else {
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vchan_cyclic_callback(&mcf_chan->edesc->vdesc);
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}
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if (!mcf_chan->edesc)
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fsl_edma_xfer_desc(mcf_chan);
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spin_unlock(&mcf_chan->vchan.lock);
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}
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}
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return IRQ_HANDLED;
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}
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static irqreturn_t mcf_edma_err_handler(int irq, void *dev_id)
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{
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struct fsl_edma_engine *mcf_edma = dev_id;
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struct edma_regs *regs = &mcf_edma->regs;
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unsigned int err, ch;
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err = ioread32(regs->errl);
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if (!err)
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return IRQ_NONE;
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for (ch = 0; ch < (EDMA_CHANNELS / 2); ch++) {
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if (err & BIT(ch)) {
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fsl_edma_disable_request(&mcf_edma->chans[ch]);
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iowrite8(EDMA_CERR_CERR(ch), regs->cerr);
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mcf_edma->chans[ch].status = DMA_ERROR;
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mcf_edma->chans[ch].idle = true;
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}
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}
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err = ioread32(regs->errh);
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if (!err)
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return IRQ_NONE;
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for (ch = (EDMA_CHANNELS / 2); ch < EDMA_CHANNELS; ch++) {
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if (err & (BIT(ch - (EDMA_CHANNELS / 2)))) {
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fsl_edma_disable_request(&mcf_edma->chans[ch]);
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iowrite8(EDMA_CERR_CERR(ch), regs->cerr);
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mcf_edma->chans[ch].status = DMA_ERROR;
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mcf_edma->chans[ch].idle = true;
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}
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}
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return IRQ_HANDLED;
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}
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static int mcf_edma_irq_init(struct platform_device *pdev,
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struct fsl_edma_engine *mcf_edma)
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{
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int ret = 0, i;
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struct resource *res;
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res = platform_get_resource_byname(pdev,
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IORESOURCE_IRQ, "edma-tx-00-15");
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if (!res)
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return -1;
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for (ret = 0, i = res->start; i <= res->end; ++i)
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ret |= request_irq(i, mcf_edma_tx_handler, 0, "eDMA", mcf_edma);
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if (ret)
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return ret;
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res = platform_get_resource_byname(pdev,
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IORESOURCE_IRQ, "edma-tx-16-55");
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if (!res)
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return -1;
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for (ret = 0, i = res->start; i <= res->end; ++i)
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ret |= request_irq(i, mcf_edma_tx_handler, 0, "eDMA", mcf_edma);
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if (ret)
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return ret;
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ret = platform_get_irq_byname(pdev, "edma-tx-56-63");
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if (ret != -ENXIO) {
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ret = request_irq(ret, mcf_edma_tx_handler,
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0, "eDMA", mcf_edma);
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if (ret)
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return ret;
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}
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ret = platform_get_irq_byname(pdev, "edma-err");
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if (ret != -ENXIO) {
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ret = request_irq(ret, mcf_edma_err_handler,
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0, "eDMA", mcf_edma);
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if (ret)
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return ret;
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}
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return 0;
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}
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static void mcf_edma_irq_free(struct platform_device *pdev,
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struct fsl_edma_engine *mcf_edma)
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{
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int irq;
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struct resource *res;
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res = platform_get_resource_byname(pdev,
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IORESOURCE_IRQ, "edma-tx-00-15");
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if (res) {
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for (irq = res->start; irq <= res->end; irq++)
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free_irq(irq, mcf_edma);
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}
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res = platform_get_resource_byname(pdev,
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IORESOURCE_IRQ, "edma-tx-16-55");
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if (res) {
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for (irq = res->start; irq <= res->end; irq++)
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free_irq(irq, mcf_edma);
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}
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irq = platform_get_irq_byname(pdev, "edma-tx-56-63");
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if (irq != -ENXIO)
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free_irq(irq, mcf_edma);
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irq = platform_get_irq_byname(pdev, "edma-err");
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if (irq != -ENXIO)
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free_irq(irq, mcf_edma);
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}
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static struct fsl_edma_drvdata mcf_data = {
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.version = v2,
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.setup_irq = mcf_edma_irq_init,
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};
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static int mcf_edma_probe(struct platform_device *pdev)
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{
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struct mcf_edma_platform_data *pdata;
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struct fsl_edma_engine *mcf_edma;
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struct fsl_edma_chan *mcf_chan;
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struct edma_regs *regs;
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struct resource *res;
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int ret, i, len, chans;
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pdata = dev_get_platdata(&pdev->dev);
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if (!pdata) {
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dev_err(&pdev->dev, "no platform data supplied\n");
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return -EINVAL;
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}
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chans = pdata->dma_channels;
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len = sizeof(*mcf_edma) + sizeof(*mcf_chan) * chans;
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mcf_edma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
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if (!mcf_edma)
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return -ENOMEM;
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mcf_edma->n_chans = chans;
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/* Set up drvdata for ColdFire edma */
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mcf_edma->drvdata = &mcf_data;
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mcf_edma->big_endian = 1;
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if (!mcf_edma->n_chans) {
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dev_info(&pdev->dev, "setting default channel number to 64");
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mcf_edma->n_chans = 64;
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}
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mutex_init(&mcf_edma->fsl_edma_mutex);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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mcf_edma->membase = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(mcf_edma->membase))
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return PTR_ERR(mcf_edma->membase);
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fsl_edma_setup_regs(mcf_edma);
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regs = &mcf_edma->regs;
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INIT_LIST_HEAD(&mcf_edma->dma_dev.channels);
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for (i = 0; i < mcf_edma->n_chans; i++) {
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struct fsl_edma_chan *mcf_chan = &mcf_edma->chans[i];
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mcf_chan->edma = mcf_edma;
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mcf_chan->slave_id = i;
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mcf_chan->idle = true;
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mcf_chan->dma_dir = DMA_NONE;
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mcf_chan->vchan.desc_free = fsl_edma_free_desc;
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vchan_init(&mcf_chan->vchan, &mcf_edma->dma_dev);
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iowrite32(0x0, ®s->tcd[i].csr);
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}
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iowrite32(~0, regs->inth);
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iowrite32(~0, regs->intl);
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ret = mcf_edma->drvdata->setup_irq(pdev, mcf_edma);
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if (ret)
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return ret;
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dma_cap_set(DMA_PRIVATE, mcf_edma->dma_dev.cap_mask);
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dma_cap_set(DMA_SLAVE, mcf_edma->dma_dev.cap_mask);
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dma_cap_set(DMA_CYCLIC, mcf_edma->dma_dev.cap_mask);
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mcf_edma->dma_dev.dev = &pdev->dev;
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mcf_edma->dma_dev.device_alloc_chan_resources =
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fsl_edma_alloc_chan_resources;
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mcf_edma->dma_dev.device_free_chan_resources =
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fsl_edma_free_chan_resources;
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mcf_edma->dma_dev.device_config = fsl_edma_slave_config;
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mcf_edma->dma_dev.device_prep_dma_cyclic =
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fsl_edma_prep_dma_cyclic;
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mcf_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg;
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mcf_edma->dma_dev.device_tx_status = fsl_edma_tx_status;
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mcf_edma->dma_dev.device_pause = fsl_edma_pause;
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mcf_edma->dma_dev.device_resume = fsl_edma_resume;
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mcf_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all;
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mcf_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending;
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mcf_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS;
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mcf_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS;
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mcf_edma->dma_dev.directions =
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BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
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mcf_edma->dma_dev.filter.fn = mcf_edma_filter_fn;
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mcf_edma->dma_dev.filter.map = pdata->slave_map;
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mcf_edma->dma_dev.filter.mapcnt = pdata->slavecnt;
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platform_set_drvdata(pdev, mcf_edma);
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ret = dma_async_device_register(&mcf_edma->dma_dev);
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if (ret) {
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dev_err(&pdev->dev,
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"Can't register Freescale eDMA engine. (%d)\n", ret);
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return ret;
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}
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/* Enable round robin arbitration */
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iowrite32(EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
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return 0;
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}
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static int mcf_edma_remove(struct platform_device *pdev)
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{
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struct fsl_edma_engine *mcf_edma = platform_get_drvdata(pdev);
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mcf_edma_irq_free(pdev, mcf_edma);
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fsl_edma_cleanup_vchan(&mcf_edma->dma_dev);
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dma_async_device_unregister(&mcf_edma->dma_dev);
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return 0;
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}
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static struct platform_driver mcf_edma_driver = {
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.driver = {
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.name = "mcf-edma",
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},
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.probe = mcf_edma_probe,
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.remove = mcf_edma_remove,
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};
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bool mcf_edma_filter_fn(struct dma_chan *chan, void *param)
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{
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if (chan->device->dev->driver == &mcf_edma_driver.driver) {
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struct fsl_edma_chan *mcf_chan = to_fsl_edma_chan(chan);
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return (mcf_chan->slave_id == (uintptr_t)param);
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}
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return false;
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}
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EXPORT_SYMBOL(mcf_edma_filter_fn);
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static int __init mcf_edma_init(void)
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{
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return platform_driver_register(&mcf_edma_driver);
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}
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subsys_initcall(mcf_edma_init);
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static void __exit mcf_edma_exit(void)
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{
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platform_driver_unregister(&mcf_edma_driver);
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}
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module_exit(mcf_edma_exit);
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MODULE_ALIAS("platform:mcf-edma");
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MODULE_DESCRIPTION("Freescale eDMA engine driver, ColdFire family");
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MODULE_LICENSE("GPL v2");
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