84 lines
3.4 KiB
Plaintext
84 lines
3.4 KiB
Plaintext
DSCR (Data Stream Control Register)
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================================================
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DSCR register in powerpc allows user to have some control of prefetch of data
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stream in the processor. Please refer to the ISA documents or related manual
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for more detailed information regarding how to use this DSCR to attain this
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control of the pefetches . This document here provides an overview of kernel
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support for DSCR, related kernel objects, it's functionalities and exported
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user interface.
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(A) Data Structures:
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(1) thread_struct:
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dscr /* Thread DSCR value */
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dscr_inherit /* Thread has changed default DSCR */
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(2) PACA:
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dscr_default /* per-CPU DSCR default value */
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(3) sysfs.c:
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dscr_default /* System DSCR default value */
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(B) Scheduler Changes:
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Scheduler will write the per-CPU DSCR default which is stored in the
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CPU's PACA value into the register if the thread has dscr_inherit value
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cleared which means that it has not changed the default DSCR till now.
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If the dscr_inherit value is set which means that it has changed the
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default DSCR value, scheduler will write the changed value which will
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now be contained in thread struct's dscr into the register instead of
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the per-CPU default PACA based DSCR value.
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NOTE: Please note here that the system wide global DSCR value never
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gets used directly in the scheduler process context switch at all.
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(C) SYSFS Interface:
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Global DSCR default: /sys/devices/system/cpu/dscr_default
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CPU specific DSCR default: /sys/devices/system/cpu/cpuN/dscr
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Changing the global DSCR default in the sysfs will change all the CPU
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specific DSCR defaults immediately in their PACA structures. Again if
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the current process has the dscr_inherit clear, it also writes the new
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value into every CPU's DSCR register right away and updates the current
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thread's DSCR value as well.
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Changing the CPU specif DSCR default value in the sysfs does exactly
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the same thing as above but unlike the global one above, it just changes
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stuff for that particular CPU instead for all the CPUs on the system.
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(D) User Space Instructions:
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The DSCR register can be accessed in the user space using any of these
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two SPR numbers available for that purpose.
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(1) Problem state SPR: 0x03 (Un-privileged, POWER8 only)
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(2) Privileged state SPR: 0x11 (Privileged)
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Accessing DSCR through privileged SPR number (0x11) from user space
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works, as it is emulated following an illegal instruction exception
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inside the kernel. Both mfspr and mtspr instructions are emulated.
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Accessing DSCR through user level SPR (0x03) from user space will first
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create a facility unavailable exception. Inside this exception handler
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all mfspr isntruction based read attempts will get emulated and returned
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where as the first mtspr instruction based write attempts will enable
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the DSCR facility for the next time around (both for read and write) by
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setting DSCR facility in the FSCR register.
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(E) Specifics about 'dscr_inherit':
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The thread struct element 'dscr_inherit' represents whether the thread
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in question has attempted and changed the DSCR itself using any of the
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following methods. This element signifies whether the thread wants to
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use the CPU default DSCR value or its own changed DSCR value in the
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kernel.
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(1) mtspr instruction (SPR number 0x03)
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(2) mtspr instruction (SPR number 0x11)
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(3) ptrace interface (Explicitly set user DSCR value)
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Any child of the process created after this event in the process inherits
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this same behaviour as well.
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