222 lines
6.2 KiB
Plaintext
222 lines
6.2 KiB
Plaintext
* Marvell EBU PCIe interfaces
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Mandatory properties:
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- compatible: one of the following values:
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marvell,armada-370-pcie
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marvell,armada-xp-pcie
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marvell,kirkwood-pcie
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- #address-cells, set to <3>
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- #size-cells, set to <2>
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- #interrupt-cells, set to <1>
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- bus-range: PCI bus numbers covered
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- device_type, set to "pci"
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- ranges: ranges for the PCI memory and I/O regions, as well as the
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MMIO registers to control the PCIe interfaces.
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In addition, the Device Tree node must have sub-nodes describing each
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PCIe interface, having the following mandatory properties:
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- reg: used only for interrupt mapping, so only the first four bytes
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are used to refer to the correct bus number and device number.
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- assigned-addresses: reference to the MMIO registers used to control
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this PCIe interface.
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- clocks: the clock associated to this PCIe interface
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- marvell,pcie-port: the physical PCIe port number
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- status: either "disabled" or "okay"
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- device_type, set to "pci"
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- #address-cells, set to <3>
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- #size-cells, set to <2>
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- #interrupt-cells, set to <1>
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- ranges, empty property.
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- interrupt-map-mask and interrupt-map, standard PCI properties to
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define the mapping of the PCIe interface to interrupt numbers.
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and the following optional properties:
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- marvell,pcie-lane: the physical PCIe lane number, for ports having
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multiple lanes. If this property is not found, we assume that the
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value is 0.
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Example:
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pcie-controller {
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compatible = "marvell,armada-xp-pcie";
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status = "disabled";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
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0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */
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0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */
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0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */
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0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */
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0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */
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0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */
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0x82000000 0 0xd0084000 0xd0084000 0 0x00002000 /* Port 1.1 registers */
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0x82000000 0 0xd0088000 0xd0088000 0 0x00002000 /* Port 1.2 registers */
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0x82000000 0 0xd008c000 0xd008c000 0 0x00002000 /* Port 1.3 registers */
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0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
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0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
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pcie@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 58>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 5>;
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status = "disabled";
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};
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pcie@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>;
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reg = <0x1000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 59>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <1>;
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clocks = <&gateclk 6>;
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status = "disabled";
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};
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pcie@3,0 {
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device_type = "pci";
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assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>;
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reg = <0x1800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 60>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <2>;
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clocks = <&gateclk 7>;
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status = "disabled";
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};
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pcie@4,0 {
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device_type = "pci";
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assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>;
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reg = <0x2000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 61>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <3>;
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clocks = <&gateclk 8>;
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status = "disabled";
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};
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pcie@5,0 {
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device_type = "pci";
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assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
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reg = <0x2800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 62>;
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marvell,pcie-port = <1>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 9>;
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status = "disabled";
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};
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pcie@6,0 {
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device_type = "pci";
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assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>;
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reg = <0x3000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 63>;
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marvell,pcie-port = <1>;
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marvell,pcie-lane = <1>;
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clocks = <&gateclk 10>;
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status = "disabled";
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};
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pcie@7,0 {
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device_type = "pci";
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assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>;
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reg = <0x3800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 64>;
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marvell,pcie-port = <1>;
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marvell,pcie-lane = <2>;
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clocks = <&gateclk 11>;
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status = "disabled";
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};
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pcie@8,0 {
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device_type = "pci";
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assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>;
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reg = <0x4000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 65>;
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marvell,pcie-port = <1>;
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marvell,pcie-lane = <3>;
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clocks = <&gateclk 12>;
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status = "disabled";
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};
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pcie@9,0 {
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device_type = "pci";
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assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>;
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reg = <0x4800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 99>;
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marvell,pcie-port = <2>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 26>;
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status = "disabled";
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};
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pcie@10,0 {
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device_type = "pci";
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assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>;
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reg = <0x5000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 103>;
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marvell,pcie-port = <3>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 27>;
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status = "disabled";
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};
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};
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