699 lines
18 KiB
C
699 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (C) 2017-2018 Socionext Inc.
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// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/mfd/tmio.h>
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#include <linux/mmc/host.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include "tmio_mmc.h"
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#define UNIPHIER_SD_CLK_CTL_DIV1024 BIT(16)
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#define UNIPHIER_SD_CLK_CTL_DIV1 BIT(10)
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#define UNIPHIER_SD_CLKCTL_OFFEN BIT(9) // auto SDCLK stop
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#define UNIPHIER_SD_CC_EXT_MODE 0x1b0
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#define UNIPHIER_SD_CC_EXT_MODE_DMA BIT(1)
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#define UNIPHIER_SD_HOST_MODE 0x1c8
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#define UNIPHIER_SD_VOLT 0x1e4
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#define UNIPHIER_SD_VOLT_MASK GENMASK(1, 0)
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#define UNIPHIER_SD_VOLT_OFF 0
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#define UNIPHIER_SD_VOLT_330 1 // 3.3V signal
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#define UNIPHIER_SD_VOLT_180 2 // 1.8V signal
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#define UNIPHIER_SD_DMA_MODE 0x410
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#define UNIPHIER_SD_DMA_MODE_DIR_MASK GENMASK(17, 16)
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#define UNIPHIER_SD_DMA_MODE_DIR_TO_DEV 0
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#define UNIPHIER_SD_DMA_MODE_DIR_FROM_DEV 1
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#define UNIPHIER_SD_DMA_MODE_WIDTH_MASK GENMASK(5, 4)
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#define UNIPHIER_SD_DMA_MODE_WIDTH_8 0
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#define UNIPHIER_SD_DMA_MODE_WIDTH_16 1
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#define UNIPHIER_SD_DMA_MODE_WIDTH_32 2
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#define UNIPHIER_SD_DMA_MODE_WIDTH_64 3
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#define UNIPHIER_SD_DMA_MODE_ADDR_INC BIT(0) // 1: inc, 0: fixed
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#define UNIPHIER_SD_DMA_CTL 0x414
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#define UNIPHIER_SD_DMA_CTL_START BIT(0) // start DMA (auto cleared)
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#define UNIPHIER_SD_DMA_RST 0x418
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#define UNIPHIER_SD_DMA_RST_CH1 BIT(9)
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#define UNIPHIER_SD_DMA_RST_CH0 BIT(8)
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#define UNIPHIER_SD_DMA_ADDR_L 0x440
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#define UNIPHIER_SD_DMA_ADDR_H 0x444
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/*
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* IP is extended to support various features: built-in DMA engine,
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* 1/1024 divisor, etc.
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*/
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#define UNIPHIER_SD_CAP_EXTENDED_IP BIT(0)
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/* RX channel of the built-in DMA controller is broken (Pro5) */
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#define UNIPHIER_SD_CAP_BROKEN_DMA_RX BIT(1)
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struct uniphier_sd_priv {
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struct tmio_mmc_data tmio_data;
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struct pinctrl *pinctrl;
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struct pinctrl_state *pinstate_default;
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struct pinctrl_state *pinstate_uhs;
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struct clk *clk;
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struct reset_control *rst;
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struct reset_control *rst_br;
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struct reset_control *rst_hw;
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struct dma_chan *chan;
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enum dma_data_direction dma_dir;
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unsigned long clk_rate;
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unsigned long caps;
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};
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static void *uniphier_sd_priv(struct tmio_mmc_host *host)
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{
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return container_of(host->pdata, struct uniphier_sd_priv, tmio_data);
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}
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static void uniphier_sd_dma_endisable(struct tmio_mmc_host *host, int enable)
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{
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sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0);
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}
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/* external DMA engine */
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static void uniphier_sd_external_dma_issue(unsigned long arg)
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{
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struct tmio_mmc_host *host = (void *)arg;
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struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
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uniphier_sd_dma_endisable(host, 1);
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dma_async_issue_pending(priv->chan);
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}
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static void uniphier_sd_external_dma_callback(void *param,
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const struct dmaengine_result *result)
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{
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struct tmio_mmc_host *host = param;
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struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
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unsigned long flags;
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dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len,
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priv->dma_dir);
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spin_lock_irqsave(&host->lock, flags);
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if (result->result == DMA_TRANS_NOERROR) {
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/*
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* When the external DMA engine is enabled, strangely enough,
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* the DATAEND flag can be asserted even if the DMA engine has
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* not been kicked yet. Enable the TMIO_STAT_DATAEND irq only
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* after we make sure the DMA engine finishes the transfer,
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* hence, in this callback.
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*/
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tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
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} else {
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host->data->error = -ETIMEDOUT;
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tmio_mmc_do_data_irq(host);
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}
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spin_unlock_irqrestore(&host->lock, flags);
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}
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static void uniphier_sd_external_dma_start(struct tmio_mmc_host *host,
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struct mmc_data *data)
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{
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struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
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enum dma_transfer_direction dma_tx_dir;
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struct dma_async_tx_descriptor *desc;
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dma_cookie_t cookie;
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int sg_len;
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if (!priv->chan)
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goto force_pio;
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if (data->flags & MMC_DATA_READ) {
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priv->dma_dir = DMA_FROM_DEVICE;
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dma_tx_dir = DMA_DEV_TO_MEM;
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} else {
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priv->dma_dir = DMA_TO_DEVICE;
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dma_tx_dir = DMA_MEM_TO_DEV;
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}
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sg_len = dma_map_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len,
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priv->dma_dir);
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if (sg_len == 0)
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goto force_pio;
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desc = dmaengine_prep_slave_sg(priv->chan, host->sg_ptr, sg_len,
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dma_tx_dir, DMA_CTRL_ACK);
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if (!desc)
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goto unmap_sg;
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desc->callback_result = uniphier_sd_external_dma_callback;
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desc->callback_param = host;
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cookie = dmaengine_submit(desc);
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if (cookie < 0)
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goto unmap_sg;
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host->dma_on = true;
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return;
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unmap_sg:
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dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len,
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priv->dma_dir);
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force_pio:
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uniphier_sd_dma_endisable(host, 0);
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}
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static void uniphier_sd_external_dma_enable(struct tmio_mmc_host *host,
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bool enable)
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{
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}
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static void uniphier_sd_external_dma_request(struct tmio_mmc_host *host,
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struct tmio_mmc_data *pdata)
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{
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struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
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struct dma_chan *chan;
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chan = dma_request_chan(mmc_dev(host->mmc), "rx-tx");
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if (IS_ERR(chan)) {
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dev_warn(mmc_dev(host->mmc),
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"failed to request DMA channel. falling back to PIO\n");
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return; /* just use PIO even for -EPROBE_DEFER */
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}
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/* this driver uses a single channel for both RX an TX */
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priv->chan = chan;
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host->chan_rx = chan;
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host->chan_tx = chan;
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tasklet_init(&host->dma_issue, uniphier_sd_external_dma_issue,
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(unsigned long)host);
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}
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static void uniphier_sd_external_dma_release(struct tmio_mmc_host *host)
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{
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struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
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if (priv->chan)
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dma_release_channel(priv->chan);
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}
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static void uniphier_sd_external_dma_abort(struct tmio_mmc_host *host)
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{
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struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
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uniphier_sd_dma_endisable(host, 0);
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if (priv->chan)
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dmaengine_terminate_sync(priv->chan);
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}
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static void uniphier_sd_external_dma_dataend(struct tmio_mmc_host *host)
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{
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uniphier_sd_dma_endisable(host, 0);
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tmio_mmc_do_data_irq(host);
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}
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static const struct tmio_mmc_dma_ops uniphier_sd_external_dma_ops = {
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.start = uniphier_sd_external_dma_start,
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.enable = uniphier_sd_external_dma_enable,
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.request = uniphier_sd_external_dma_request,
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.release = uniphier_sd_external_dma_release,
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.abort = uniphier_sd_external_dma_abort,
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.dataend = uniphier_sd_external_dma_dataend,
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};
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static void uniphier_sd_internal_dma_issue(unsigned long arg)
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{
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struct tmio_mmc_host *host = (void *)arg;
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unsigned long flags;
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spin_lock_irqsave(&host->lock, flags);
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tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
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spin_unlock_irqrestore(&host->lock, flags);
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uniphier_sd_dma_endisable(host, 1);
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writel(UNIPHIER_SD_DMA_CTL_START, host->ctl + UNIPHIER_SD_DMA_CTL);
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}
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static void uniphier_sd_internal_dma_start(struct tmio_mmc_host *host,
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struct mmc_data *data)
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{
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struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
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struct scatterlist *sg = host->sg_ptr;
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dma_addr_t dma_addr;
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unsigned int dma_mode_dir;
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u32 dma_mode;
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int sg_len;
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if ((data->flags & MMC_DATA_READ) && !host->chan_rx)
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goto force_pio;
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if (WARN_ON(host->sg_len != 1))
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goto force_pio;
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if (!IS_ALIGNED(sg->offset, 8))
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goto force_pio;
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if (data->flags & MMC_DATA_READ) {
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priv->dma_dir = DMA_FROM_DEVICE;
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dma_mode_dir = UNIPHIER_SD_DMA_MODE_DIR_FROM_DEV;
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} else {
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priv->dma_dir = DMA_TO_DEVICE;
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dma_mode_dir = UNIPHIER_SD_DMA_MODE_DIR_TO_DEV;
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}
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sg_len = dma_map_sg(mmc_dev(host->mmc), sg, 1, priv->dma_dir);
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if (sg_len == 0)
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goto force_pio;
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dma_mode = FIELD_PREP(UNIPHIER_SD_DMA_MODE_DIR_MASK, dma_mode_dir);
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dma_mode |= FIELD_PREP(UNIPHIER_SD_DMA_MODE_WIDTH_MASK,
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UNIPHIER_SD_DMA_MODE_WIDTH_64);
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dma_mode |= UNIPHIER_SD_DMA_MODE_ADDR_INC;
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writel(dma_mode, host->ctl + UNIPHIER_SD_DMA_MODE);
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dma_addr = sg_dma_address(data->sg);
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writel(lower_32_bits(dma_addr), host->ctl + UNIPHIER_SD_DMA_ADDR_L);
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writel(upper_32_bits(dma_addr), host->ctl + UNIPHIER_SD_DMA_ADDR_H);
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host->dma_on = true;
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return;
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force_pio:
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uniphier_sd_dma_endisable(host, 0);
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}
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static void uniphier_sd_internal_dma_enable(struct tmio_mmc_host *host,
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bool enable)
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{
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}
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static void uniphier_sd_internal_dma_request(struct tmio_mmc_host *host,
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struct tmio_mmc_data *pdata)
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{
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struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
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/*
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* Due to a hardware bug, Pro5 cannot use DMA for RX.
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* We can still use DMA for TX, but PIO for RX.
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*/
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if (!(priv->caps & UNIPHIER_SD_CAP_BROKEN_DMA_RX))
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host->chan_rx = (void *)0xdeadbeaf;
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host->chan_tx = (void *)0xdeadbeaf;
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tasklet_init(&host->dma_issue, uniphier_sd_internal_dma_issue,
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(unsigned long)host);
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}
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static void uniphier_sd_internal_dma_release(struct tmio_mmc_host *host)
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{
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/* Each value is set to zero to assume "disabling" each DMA */
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host->chan_rx = NULL;
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host->chan_tx = NULL;
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}
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static void uniphier_sd_internal_dma_abort(struct tmio_mmc_host *host)
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{
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u32 tmp;
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uniphier_sd_dma_endisable(host, 0);
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tmp = readl(host->ctl + UNIPHIER_SD_DMA_RST);
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tmp &= ~(UNIPHIER_SD_DMA_RST_CH1 | UNIPHIER_SD_DMA_RST_CH0);
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writel(tmp, host->ctl + UNIPHIER_SD_DMA_RST);
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tmp |= UNIPHIER_SD_DMA_RST_CH1 | UNIPHIER_SD_DMA_RST_CH0;
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writel(tmp, host->ctl + UNIPHIER_SD_DMA_RST);
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}
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static void uniphier_sd_internal_dma_dataend(struct tmio_mmc_host *host)
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{
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struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
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uniphier_sd_dma_endisable(host, 0);
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dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, 1, priv->dma_dir);
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tmio_mmc_do_data_irq(host);
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}
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static const struct tmio_mmc_dma_ops uniphier_sd_internal_dma_ops = {
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.start = uniphier_sd_internal_dma_start,
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.enable = uniphier_sd_internal_dma_enable,
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.request = uniphier_sd_internal_dma_request,
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.release = uniphier_sd_internal_dma_release,
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.abort = uniphier_sd_internal_dma_abort,
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.dataend = uniphier_sd_internal_dma_dataend,
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};
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static int uniphier_sd_clk_enable(struct tmio_mmc_host *host)
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{
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struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
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struct mmc_host *mmc = host->mmc;
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int ret;
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ret = clk_prepare_enable(priv->clk);
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if (ret)
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return ret;
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ret = clk_set_rate(priv->clk, ULONG_MAX);
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if (ret)
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goto disable_clk;
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priv->clk_rate = clk_get_rate(priv->clk);
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/* If max-frequency property is set, use it. */
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if (!mmc->f_max)
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mmc->f_max = priv->clk_rate;
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/*
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* 1/512 is the finest divisor in the original IP. Newer versions
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* also supports 1/1024 divisor. (UniPhier-specific extension)
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*/
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if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)
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mmc->f_min = priv->clk_rate / 1024;
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else
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mmc->f_min = priv->clk_rate / 512;
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ret = reset_control_deassert(priv->rst);
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if (ret)
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goto disable_clk;
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ret = reset_control_deassert(priv->rst_br);
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if (ret)
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goto assert_rst;
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return 0;
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assert_rst:
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reset_control_assert(priv->rst);
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disable_clk:
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clk_disable_unprepare(priv->clk);
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return ret;
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}
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static void uniphier_sd_clk_disable(struct tmio_mmc_host *host)
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{
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struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
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reset_control_assert(priv->rst_br);
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reset_control_assert(priv->rst);
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clk_disable_unprepare(priv->clk);
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}
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static void uniphier_sd_hw_reset(struct tmio_mmc_host *host)
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{
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struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
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reset_control_assert(priv->rst_hw);
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/* For eMMC, minimum is 1us but give it 9us for good measure */
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udelay(9);
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reset_control_deassert(priv->rst_hw);
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/* For eMMC, minimum is 200us but give it 300us for good measure */
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usleep_range(300, 1000);
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}
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static void uniphier_sd_set_clock(struct tmio_mmc_host *host,
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unsigned int clock)
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{
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struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
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unsigned long divisor;
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u32 tmp;
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tmp = readl(host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
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/* stop the clock before changing its rate to avoid a glitch signal */
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tmp &= ~CLK_CTL_SCLKEN;
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writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
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if (clock == 0)
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return;
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tmp &= ~UNIPHIER_SD_CLK_CTL_DIV1024;
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tmp &= ~UNIPHIER_SD_CLK_CTL_DIV1;
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tmp &= ~CLK_CTL_DIV_MASK;
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divisor = priv->clk_rate / clock;
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/*
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* In the original IP, bit[7:0] represents the divisor.
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* bit7 set: 1/512, ... bit0 set:1/4, all bits clear: 1/2
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*
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* The IP does not define a way to achieve 1/1. For UniPhier variants,
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* bit10 is used for 1/1. Newer versions of UniPhier variants use
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* bit16 for 1/1024.
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*/
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if (divisor <= 1)
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tmp |= UNIPHIER_SD_CLK_CTL_DIV1;
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else if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP && divisor > 512)
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tmp |= UNIPHIER_SD_CLK_CTL_DIV1024;
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else
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tmp |= roundup_pow_of_two(divisor) >> 2;
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writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
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tmp |= CLK_CTL_SCLKEN;
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writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
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}
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static void uniphier_sd_host_init(struct tmio_mmc_host *host)
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{
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struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
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u32 val;
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/*
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* Connected to 32bit AXI.
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* This register holds settings for SoC-specific internal bus
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* connection. What is worse, the register spec was changed,
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* breaking the backward compatibility. Write an appropriate
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* value depending on a flag associated with a compatible string.
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*/
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if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)
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val = 0x00000101;
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else
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val = 0x00000000;
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writel(val, host->ctl + UNIPHIER_SD_HOST_MODE);
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val = 0;
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/*
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* If supported, the controller can automatically
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* enable/disable the clock line to the card.
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*/
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if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)
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val |= UNIPHIER_SD_CLKCTL_OFFEN;
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writel(val, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
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}
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static int uniphier_sd_start_signal_voltage_switch(struct mmc_host *mmc,
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struct mmc_ios *ios)
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{
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struct tmio_mmc_host *host = mmc_priv(mmc);
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struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
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struct pinctrl_state *pinstate;
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u32 val, tmp;
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switch (ios->signal_voltage) {
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case MMC_SIGNAL_VOLTAGE_330:
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val = UNIPHIER_SD_VOLT_330;
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pinstate = priv->pinstate_default;
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break;
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case MMC_SIGNAL_VOLTAGE_180:
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val = UNIPHIER_SD_VOLT_180;
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pinstate = priv->pinstate_uhs;
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break;
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default:
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return -ENOTSUPP;
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}
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|
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tmp = readl(host->ctl + UNIPHIER_SD_VOLT);
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tmp &= ~UNIPHIER_SD_VOLT_MASK;
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tmp |= FIELD_PREP(UNIPHIER_SD_VOLT_MASK, val);
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writel(tmp, host->ctl + UNIPHIER_SD_VOLT);
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pinctrl_select_state(priv->pinctrl, pinstate);
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return 0;
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}
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|
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static int uniphier_sd_uhs_init(struct tmio_mmc_host *host,
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struct uniphier_sd_priv *priv)
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{
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priv->pinctrl = devm_pinctrl_get(mmc_dev(host->mmc));
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if (IS_ERR(priv->pinctrl))
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return PTR_ERR(priv->pinctrl);
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|
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priv->pinstate_default = pinctrl_lookup_state(priv->pinctrl,
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PINCTRL_STATE_DEFAULT);
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if (IS_ERR(priv->pinstate_default))
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return PTR_ERR(priv->pinstate_default);
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|
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priv->pinstate_uhs = pinctrl_lookup_state(priv->pinctrl, "uhs");
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if (IS_ERR(priv->pinstate_uhs))
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return PTR_ERR(priv->pinstate_uhs);
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|
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host->ops.start_signal_voltage_switch =
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uniphier_sd_start_signal_voltage_switch;
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|
|
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return 0;
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}
|
|
|
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static int uniphier_sd_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
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struct uniphier_sd_priv *priv;
|
|
struct tmio_mmc_data *tmio_data;
|
|
struct tmio_mmc_host *host;
|
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int irq, ret;
|
|
|
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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dev_err(dev, "failed to get IRQ number");
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|
return irq;
|
|
}
|
|
|
|
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
|
if (!priv)
|
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return -ENOMEM;
|
|
|
|
priv->caps = (unsigned long)of_device_get_match_data(dev);
|
|
|
|
priv->clk = devm_clk_get(dev, NULL);
|
|
if (IS_ERR(priv->clk)) {
|
|
dev_err(dev, "failed to get clock\n");
|
|
return PTR_ERR(priv->clk);
|
|
}
|
|
|
|
priv->rst = devm_reset_control_get_shared(dev, "host");
|
|
if (IS_ERR(priv->rst)) {
|
|
dev_err(dev, "failed to get host reset\n");
|
|
return PTR_ERR(priv->rst);
|
|
}
|
|
|
|
/* old version has one more reset */
|
|
if (!(priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)) {
|
|
priv->rst_br = devm_reset_control_get_shared(dev, "bridge");
|
|
if (IS_ERR(priv->rst_br)) {
|
|
dev_err(dev, "failed to get bridge reset\n");
|
|
return PTR_ERR(priv->rst_br);
|
|
}
|
|
}
|
|
|
|
tmio_data = &priv->tmio_data;
|
|
tmio_data->flags |= TMIO_MMC_32BIT_DATA_PORT;
|
|
|
|
host = tmio_mmc_host_alloc(pdev, tmio_data);
|
|
if (IS_ERR(host))
|
|
return PTR_ERR(host);
|
|
|
|
if (host->mmc->caps & MMC_CAP_HW_RESET) {
|
|
priv->rst_hw = devm_reset_control_get_exclusive(dev, "hw");
|
|
if (IS_ERR(priv->rst_hw)) {
|
|
dev_err(dev, "failed to get hw reset\n");
|
|
ret = PTR_ERR(priv->rst_hw);
|
|
goto free_host;
|
|
}
|
|
host->hw_reset = uniphier_sd_hw_reset;
|
|
}
|
|
|
|
if (host->mmc->caps & MMC_CAP_UHS) {
|
|
ret = uniphier_sd_uhs_init(host, priv);
|
|
if (ret) {
|
|
dev_warn(dev,
|
|
"failed to setup UHS (error %d). Disabling UHS.",
|
|
ret);
|
|
host->mmc->caps &= ~MMC_CAP_UHS;
|
|
}
|
|
}
|
|
|
|
ret = devm_request_irq(dev, irq, tmio_mmc_irq, IRQF_SHARED,
|
|
dev_name(dev), host);
|
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if (ret)
|
|
goto free_host;
|
|
|
|
if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)
|
|
host->dma_ops = &uniphier_sd_internal_dma_ops;
|
|
else
|
|
host->dma_ops = &uniphier_sd_external_dma_ops;
|
|
|
|
host->bus_shift = 1;
|
|
host->clk_enable = uniphier_sd_clk_enable;
|
|
host->clk_disable = uniphier_sd_clk_disable;
|
|
host->set_clock = uniphier_sd_set_clock;
|
|
|
|
ret = uniphier_sd_clk_enable(host);
|
|
if (ret)
|
|
goto free_host;
|
|
|
|
uniphier_sd_host_init(host);
|
|
|
|
tmio_data->ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34;
|
|
if (host->mmc->caps & MMC_CAP_UHS)
|
|
tmio_data->ocr_mask |= MMC_VDD_165_195;
|
|
|
|
tmio_data->max_segs = 1;
|
|
tmio_data->max_blk_count = U16_MAX;
|
|
|
|
ret = tmio_mmc_host_probe(host);
|
|
if (ret)
|
|
goto free_host;
|
|
|
|
return 0;
|
|
|
|
free_host:
|
|
tmio_mmc_host_free(host);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int uniphier_sd_remove(struct platform_device *pdev)
|
|
{
|
|
struct tmio_mmc_host *host = platform_get_drvdata(pdev);
|
|
|
|
tmio_mmc_host_remove(host);
|
|
uniphier_sd_clk_disable(host);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id uniphier_sd_match[] = {
|
|
{
|
|
.compatible = "socionext,uniphier-sd-v2.91",
|
|
},
|
|
{
|
|
.compatible = "socionext,uniphier-sd-v3.1",
|
|
.data = (void *)(UNIPHIER_SD_CAP_EXTENDED_IP |
|
|
UNIPHIER_SD_CAP_BROKEN_DMA_RX),
|
|
},
|
|
{
|
|
.compatible = "socionext,uniphier-sd-v3.1.1",
|
|
.data = (void *)UNIPHIER_SD_CAP_EXTENDED_IP,
|
|
},
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, uniphier_sd_match);
|
|
|
|
static struct platform_driver uniphier_sd_driver = {
|
|
.probe = uniphier_sd_probe,
|
|
.remove = uniphier_sd_remove,
|
|
.driver = {
|
|
.name = "uniphier-sd",
|
|
.of_match_table = uniphier_sd_match,
|
|
},
|
|
};
|
|
module_platform_driver(uniphier_sd_driver);
|
|
|
|
MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
|
|
MODULE_DESCRIPTION("UniPhier SD/eMMC host controller driver");
|
|
MODULE_LICENSE("GPL v2");
|