499 lines
12 KiB
C
499 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Secure Digital Host Controller
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//
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// Copyright (C) 2018 Spreadtrum, Inc.
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// Author: Chunyan Zhang <chunyan.zhang@unisoc.com>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/highmem.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_gpio.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regulator/consumer.h>
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#include <linux/slab.h>
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#include "sdhci-pltfm.h"
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/* SDHCI_ARGUMENT2 register high 16bit */
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#define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16)
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#define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208
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#define SDHCIBSPRD_IT_WR_DLY_INV BIT(5)
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#define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13)
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#define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21)
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#define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29)
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#define SDHCI_SPRD_REG_32_BUSY_POSI 0x250
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#define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25)
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#define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24)
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#define SDHCI_SPRD_REG_DEBOUNCE 0x28C
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#define SDHCI_SPRD_BIT_DLL_BAK BIT(0)
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#define SDHCI_SPRD_BIT_DLL_VAL BIT(1)
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#define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B
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/* SDHCI_HOST_CONTROL2 */
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#define SDHCI_SPRD_CTRL_HS200 0x0005
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#define SDHCI_SPRD_CTRL_HS400 0x0006
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/*
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* According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is
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* reserved, and only used on Spreadtrum's design, the hardware cannot work
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* if this bit is cleared.
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* 1 : normal work
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* 0 : hardware reset
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*/
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#define SDHCI_HW_RESET_CARD BIT(3)
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#define SDHCI_SPRD_MAX_CUR 0xFFFFFF
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#define SDHCI_SPRD_CLK_MAX_DIV 1023
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#define SDHCI_SPRD_CLK_DEF_RATE 26000000
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struct sdhci_sprd_host {
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u32 version;
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struct clk *clk_sdio;
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struct clk *clk_enable;
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u32 base_rate;
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int flags; /* backup of host attribute */
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};
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#define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host))
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static void sdhci_sprd_init_config(struct sdhci_host *host)
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{
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u16 val;
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/* set dll backup mode */
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val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE);
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val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL;
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sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE);
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}
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static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg)
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{
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if (unlikely(reg == SDHCI_MAX_CURRENT))
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return SDHCI_SPRD_MAX_CUR;
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return readl_relaxed(host->ioaddr + reg);
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}
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static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg)
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{
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/* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */
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if (unlikely(reg == SDHCI_MAX_CURRENT))
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return;
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if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE))
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val = val & SDHCI_SPRD_INT_SIGNAL_MASK;
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writel_relaxed(val, host->ioaddr + reg);
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}
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static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg)
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{
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/* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */
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if (unlikely(reg == SDHCI_BLOCK_COUNT))
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return;
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writew_relaxed(val, host->ioaddr + reg);
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}
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static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg)
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{
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/*
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* Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the
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* standard specification, sdhci_reset() write this register directly
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* without checking other reserved bits, that will clear BIT(3) which
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* is defined as hardware reset on Spreadtrum's platform and clearing
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* it by mistake will lead the card not work. So here we need to work
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* around it.
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*/
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if (unlikely(reg == SDHCI_SOFTWARE_RESET)) {
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if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD)
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val |= SDHCI_HW_RESET_CARD;
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}
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writeb_relaxed(val, host->ioaddr + reg);
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}
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static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host)
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{
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u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
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ctrl &= ~SDHCI_CLOCK_CARD_EN;
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sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
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}
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static inline void
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sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en)
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{
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u32 dll_dly_offset;
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dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET);
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if (en)
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dll_dly_offset |= mask;
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else
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dll_dly_offset &= ~mask;
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sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET);
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}
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static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk)
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{
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u32 div;
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/* select 2x clock source */
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if (base_clk <= clk * 2)
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return 0;
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div = (u32) (base_clk / (clk * 2));
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if ((base_clk / div) > (clk * 2))
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div++;
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if (div > SDHCI_SPRD_CLK_MAX_DIV)
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div = SDHCI_SPRD_CLK_MAX_DIV;
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if (div % 2)
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div = (div + 1) / 2;
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else
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div = div / 2;
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return div;
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}
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static inline void _sdhci_sprd_set_clock(struct sdhci_host *host,
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unsigned int clk)
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{
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struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
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u32 div, val, mask;
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div = sdhci_sprd_calc_div(sprd_host->base_rate, clk);
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clk |= ((div & 0x300) >> 2) | ((div & 0xFF) << 8);
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sdhci_enable_clk(host, clk);
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/* enable auto gate sdhc_enable_auto_gate */
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val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI);
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mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN |
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SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN;
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if (mask != (val & mask)) {
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val |= mask;
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sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI);
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}
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}
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static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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bool en = false;
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if (clock == 0) {
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sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
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} else if (clock != host->clock) {
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sdhci_sprd_sd_clk_off(host);
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_sdhci_sprd_set_clock(host, clock);
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if (clock <= 400000)
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en = true;
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sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV |
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SDHCI_SPRD_BIT_POSRD_DLY_INV, en);
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} else {
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_sdhci_sprd_set_clock(host, clock);
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}
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}
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static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host)
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{
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struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
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return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX);
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}
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static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host)
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{
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return 400000;
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}
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static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host,
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unsigned int timing)
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{
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u16 ctrl_2;
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if (timing == host->timing)
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return;
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ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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/* Select Bus Speed Mode for host */
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ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
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switch (timing) {
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case MMC_TIMING_UHS_SDR12:
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ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
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break;
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case MMC_TIMING_MMC_HS:
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case MMC_TIMING_SD_HS:
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case MMC_TIMING_UHS_SDR25:
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ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
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break;
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case MMC_TIMING_UHS_SDR50:
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ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
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break;
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case MMC_TIMING_UHS_SDR104:
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ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
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break;
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case MMC_TIMING_UHS_DDR50:
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case MMC_TIMING_MMC_DDR52:
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ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
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break;
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case MMC_TIMING_MMC_HS200:
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ctrl_2 |= SDHCI_SPRD_CTRL_HS200;
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break;
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case MMC_TIMING_MMC_HS400:
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ctrl_2 |= SDHCI_SPRD_CTRL_HS400;
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break;
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default:
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break;
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}
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sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
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}
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static void sdhci_sprd_hw_reset(struct sdhci_host *host)
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{
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int val;
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/*
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* Note: don't use sdhci_writeb() API here since it is redirected to
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* sdhci_sprd_writeb() in which we have a workaround for
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* SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can
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* not be cleared.
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*/
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val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET);
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val &= ~SDHCI_HW_RESET_CARD;
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writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET);
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/* wait for 10 us */
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usleep_range(10, 20);
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val |= SDHCI_HW_RESET_CARD;
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writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET);
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usleep_range(300, 500);
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}
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static struct sdhci_ops sdhci_sprd_ops = {
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.read_l = sdhci_sprd_readl,
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.write_l = sdhci_sprd_writel,
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.write_b = sdhci_sprd_writeb,
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.set_clock = sdhci_sprd_set_clock,
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.get_max_clock = sdhci_sprd_get_max_clock,
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.get_min_clock = sdhci_sprd_get_min_clock,
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.set_bus_width = sdhci_set_bus_width,
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.reset = sdhci_reset,
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.set_uhs_signaling = sdhci_sprd_set_uhs_signaling,
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.hw_reset = sdhci_sprd_hw_reset,
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};
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static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq)
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{
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struct sdhci_host *host = mmc_priv(mmc);
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struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
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host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23;
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/*
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* From version 4.10 onward, ARGUMENT2 register is also as 32-bit
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* block count register which doesn't support stuff bits of
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* CMD23 argument on Spreadtrum's sd host controller.
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*/
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if (host->version >= SDHCI_SPEC_410 &&
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mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) &&
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(host->flags & SDHCI_AUTO_CMD23))
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host->flags &= ~SDHCI_AUTO_CMD23;
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sdhci_request(mmc, mrq);
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}
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static const struct sdhci_pltfm_data sdhci_sprd_pdata = {
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.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK,
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.quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
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SDHCI_QUIRK2_USE_32BIT_BLK_CNT,
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.ops = &sdhci_sprd_ops,
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};
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static int sdhci_sprd_probe(struct platform_device *pdev)
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{
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struct sdhci_host *host;
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struct sdhci_sprd_host *sprd_host;
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struct clk *clk;
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int ret = 0;
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host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host));
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if (IS_ERR(host))
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return PTR_ERR(host);
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host->dma_mask = DMA_BIT_MASK(64);
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pdev->dev.dma_mask = &host->dma_mask;
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host->mmc_host_ops.request = sdhci_sprd_request;
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host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
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MMC_CAP_ERASE | MMC_CAP_CMD23;
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ret = mmc_of_parse(host->mmc);
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if (ret)
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goto pltfm_free;
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sprd_host = TO_SPRD_HOST(host);
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clk = devm_clk_get(&pdev->dev, "sdio");
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if (IS_ERR(clk)) {
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ret = PTR_ERR(clk);
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goto pltfm_free;
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}
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sprd_host->clk_sdio = clk;
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sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio);
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if (!sprd_host->base_rate)
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sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE;
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clk = devm_clk_get(&pdev->dev, "enable");
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if (IS_ERR(clk)) {
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ret = PTR_ERR(clk);
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goto pltfm_free;
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}
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sprd_host->clk_enable = clk;
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ret = clk_prepare_enable(sprd_host->clk_sdio);
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if (ret)
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goto pltfm_free;
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clk_prepare_enable(sprd_host->clk_enable);
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if (ret)
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goto clk_disable;
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sdhci_sprd_init_config(host);
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host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
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sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >>
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SDHCI_VENDOR_VER_SHIFT);
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pm_runtime_get_noresume(&pdev->dev);
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pm_runtime_set_active(&pdev->dev);
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pm_runtime_enable(&pdev->dev);
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pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
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pm_runtime_use_autosuspend(&pdev->dev);
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pm_suspend_ignore_children(&pdev->dev, 1);
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sdhci_enable_v4_mode(host);
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ret = sdhci_setup_host(host);
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if (ret)
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goto pm_runtime_disable;
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sprd_host->flags = host->flags;
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ret = __sdhci_add_host(host);
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if (ret)
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goto err_cleanup_host;
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pm_runtime_mark_last_busy(&pdev->dev);
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pm_runtime_put_autosuspend(&pdev->dev);
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return 0;
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err_cleanup_host:
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sdhci_cleanup_host(host);
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pm_runtime_disable:
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pm_runtime_disable(&pdev->dev);
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pm_runtime_set_suspended(&pdev->dev);
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clk_disable_unprepare(sprd_host->clk_enable);
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clk_disable:
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clk_disable_unprepare(sprd_host->clk_sdio);
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pltfm_free:
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sdhci_pltfm_free(pdev);
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return ret;
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}
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static int sdhci_sprd_remove(struct platform_device *pdev)
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{
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struct sdhci_host *host = platform_get_drvdata(pdev);
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struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
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struct mmc_host *mmc = host->mmc;
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mmc_remove_host(mmc);
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clk_disable_unprepare(sprd_host->clk_sdio);
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clk_disable_unprepare(sprd_host->clk_enable);
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mmc_free_host(mmc);
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return 0;
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}
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static const struct of_device_id sdhci_sprd_of_match[] = {
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{ .compatible = "sprd,sdhci-r11", },
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{ }
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};
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MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match);
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#ifdef CONFIG_PM
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static int sdhci_sprd_runtime_suspend(struct device *dev)
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{
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struct sdhci_host *host = dev_get_drvdata(dev);
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struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
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sdhci_runtime_suspend_host(host);
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clk_disable_unprepare(sprd_host->clk_sdio);
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clk_disable_unprepare(sprd_host->clk_enable);
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return 0;
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}
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static int sdhci_sprd_runtime_resume(struct device *dev)
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{
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struct sdhci_host *host = dev_get_drvdata(dev);
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struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
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int ret;
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ret = clk_prepare_enable(sprd_host->clk_enable);
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if (ret)
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return ret;
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ret = clk_prepare_enable(sprd_host->clk_sdio);
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if (ret) {
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clk_disable_unprepare(sprd_host->clk_enable);
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return ret;
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}
|
|
|
|
sdhci_runtime_resume_host(host);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static const struct dev_pm_ops sdhci_sprd_pm_ops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
|
pm_runtime_force_resume)
|
|
SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend,
|
|
sdhci_sprd_runtime_resume, NULL)
|
|
};
|
|
|
|
static struct platform_driver sdhci_sprd_driver = {
|
|
.probe = sdhci_sprd_probe,
|
|
.remove = sdhci_sprd_remove,
|
|
.driver = {
|
|
.name = "sdhci_sprd_r11",
|
|
.of_match_table = of_match_ptr(sdhci_sprd_of_match),
|
|
.pm = &sdhci_sprd_pm_ops,
|
|
},
|
|
};
|
|
module_platform_driver(sdhci_sprd_driver);
|
|
|
|
MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("platform:sdhci-sprd-r11");
|