290 lines
6.8 KiB
C
290 lines
6.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Timberdale FPGA GPIO driver
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* Author: Mocean Laboratories
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* Copyright (c) 2009 Intel Corporation
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*/
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/* Supports:
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* Timberdale FPGA GPIO
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*/
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#include <linux/init.h>
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#include <linux/gpio/driver.h>
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#include <linux/platform_device.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/timb_gpio.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#define DRIVER_NAME "timb-gpio"
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#define TGPIOVAL 0x00
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#define TGPIODIR 0x04
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#define TGPIO_IER 0x08
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#define TGPIO_ISR 0x0c
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#define TGPIO_IPR 0x10
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#define TGPIO_ICR 0x14
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#define TGPIO_FLR 0x18
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#define TGPIO_LVR 0x1c
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#define TGPIO_VER 0x20
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#define TGPIO_BFLR 0x24
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struct timbgpio {
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void __iomem *membase;
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spinlock_t lock; /* mutual exclusion */
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struct gpio_chip gpio;
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int irq_base;
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unsigned long last_ier;
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};
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static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
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unsigned offset, bool enabled)
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{
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struct timbgpio *tgpio = gpiochip_get_data(gpio);
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u32 reg;
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spin_lock(&tgpio->lock);
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reg = ioread32(tgpio->membase + offset);
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if (enabled)
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reg |= (1 << index);
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else
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reg &= ~(1 << index);
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iowrite32(reg, tgpio->membase + offset);
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spin_unlock(&tgpio->lock);
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return 0;
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}
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static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
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{
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return timbgpio_update_bit(gpio, nr, TGPIODIR, true);
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}
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static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr)
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{
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struct timbgpio *tgpio = gpiochip_get_data(gpio);
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u32 value;
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value = ioread32(tgpio->membase + TGPIOVAL);
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return (value & (1 << nr)) ? 1 : 0;
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}
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static int timbgpio_gpio_direction_output(struct gpio_chip *gpio,
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unsigned nr, int val)
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{
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return timbgpio_update_bit(gpio, nr, TGPIODIR, false);
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}
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static void timbgpio_gpio_set(struct gpio_chip *gpio,
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unsigned nr, int val)
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{
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timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0);
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}
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static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset)
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{
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struct timbgpio *tgpio = gpiochip_get_data(gpio);
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if (tgpio->irq_base <= 0)
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return -EINVAL;
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return tgpio->irq_base + offset;
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}
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/*
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* GPIO IRQ
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*/
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static void timbgpio_irq_disable(struct irq_data *d)
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{
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struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
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int offset = d->irq - tgpio->irq_base;
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unsigned long flags;
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spin_lock_irqsave(&tgpio->lock, flags);
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tgpio->last_ier &= ~(1UL << offset);
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iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
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spin_unlock_irqrestore(&tgpio->lock, flags);
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}
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static void timbgpio_irq_enable(struct irq_data *d)
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{
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struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
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int offset = d->irq - tgpio->irq_base;
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unsigned long flags;
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spin_lock_irqsave(&tgpio->lock, flags);
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tgpio->last_ier |= 1UL << offset;
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iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
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spin_unlock_irqrestore(&tgpio->lock, flags);
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}
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static int timbgpio_irq_type(struct irq_data *d, unsigned trigger)
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{
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struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
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int offset = d->irq - tgpio->irq_base;
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unsigned long flags;
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u32 lvr, flr, bflr = 0;
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u32 ver;
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int ret = 0;
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if (offset < 0 || offset > tgpio->gpio.ngpio)
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return -EINVAL;
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ver = ioread32(tgpio->membase + TGPIO_VER);
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spin_lock_irqsave(&tgpio->lock, flags);
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lvr = ioread32(tgpio->membase + TGPIO_LVR);
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flr = ioread32(tgpio->membase + TGPIO_FLR);
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if (ver > 2)
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bflr = ioread32(tgpio->membase + TGPIO_BFLR);
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if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
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bflr &= ~(1 << offset);
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flr &= ~(1 << offset);
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if (trigger & IRQ_TYPE_LEVEL_HIGH)
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lvr |= 1 << offset;
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else
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lvr &= ~(1 << offset);
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}
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if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
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if (ver < 3) {
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ret = -EINVAL;
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goto out;
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} else {
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flr |= 1 << offset;
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bflr |= 1 << offset;
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}
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} else {
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bflr &= ~(1 << offset);
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flr |= 1 << offset;
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if (trigger & IRQ_TYPE_EDGE_FALLING)
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lvr &= ~(1 << offset);
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else
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lvr |= 1 << offset;
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}
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iowrite32(lvr, tgpio->membase + TGPIO_LVR);
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iowrite32(flr, tgpio->membase + TGPIO_FLR);
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if (ver > 2)
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iowrite32(bflr, tgpio->membase + TGPIO_BFLR);
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iowrite32(1 << offset, tgpio->membase + TGPIO_ICR);
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out:
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spin_unlock_irqrestore(&tgpio->lock, flags);
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return ret;
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}
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static void timbgpio_irq(struct irq_desc *desc)
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{
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struct timbgpio *tgpio = irq_desc_get_handler_data(desc);
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struct irq_data *data = irq_desc_get_irq_data(desc);
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unsigned long ipr;
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int offset;
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data->chip->irq_ack(data);
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ipr = ioread32(tgpio->membase + TGPIO_IPR);
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iowrite32(ipr, tgpio->membase + TGPIO_ICR);
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/*
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* Some versions of the hardware trash the IER register if more than
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* one interrupt is received simultaneously.
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*/
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iowrite32(0, tgpio->membase + TGPIO_IER);
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for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio)
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generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset));
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iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
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}
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static struct irq_chip timbgpio_irqchip = {
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.name = "GPIO",
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.irq_enable = timbgpio_irq_enable,
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.irq_disable = timbgpio_irq_disable,
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.irq_set_type = timbgpio_irq_type,
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};
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static int timbgpio_probe(struct platform_device *pdev)
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{
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int err, i;
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struct device *dev = &pdev->dev;
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struct gpio_chip *gc;
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struct timbgpio *tgpio;
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struct timbgpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
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int irq = platform_get_irq(pdev, 0);
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if (!pdata || pdata->nr_pins > 32) {
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dev_err(dev, "Invalid platform data\n");
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return -EINVAL;
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}
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tgpio = devm_kzalloc(dev, sizeof(*tgpio), GFP_KERNEL);
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if (!tgpio)
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return -EINVAL;
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tgpio->irq_base = pdata->irq_base;
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spin_lock_init(&tgpio->lock);
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tgpio->membase = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(tgpio->membase))
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return PTR_ERR(tgpio->membase);
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gc = &tgpio->gpio;
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gc->label = dev_name(&pdev->dev);
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gc->owner = THIS_MODULE;
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gc->parent = &pdev->dev;
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gc->direction_input = timbgpio_gpio_direction_input;
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gc->get = timbgpio_gpio_get;
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gc->direction_output = timbgpio_gpio_direction_output;
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gc->set = timbgpio_gpio_set;
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gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL;
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gc->dbg_show = NULL;
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gc->base = pdata->gpio_base;
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gc->ngpio = pdata->nr_pins;
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gc->can_sleep = false;
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err = devm_gpiochip_add_data(&pdev->dev, gc, tgpio);
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if (err)
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return err;
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platform_set_drvdata(pdev, tgpio);
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/* make sure to disable interrupts */
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iowrite32(0x0, tgpio->membase + TGPIO_IER);
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if (irq < 0 || tgpio->irq_base <= 0)
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return 0;
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for (i = 0; i < pdata->nr_pins; i++) {
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irq_set_chip_and_handler(tgpio->irq_base + i,
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&timbgpio_irqchip, handle_simple_irq);
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irq_set_chip_data(tgpio->irq_base + i, tgpio);
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irq_clear_status_flags(tgpio->irq_base + i, IRQ_NOREQUEST | IRQ_NOPROBE);
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}
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irq_set_chained_handler_and_data(irq, timbgpio_irq, tgpio);
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return 0;
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}
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static struct platform_driver timbgpio_platform_driver = {
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.driver = {
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.name = DRIVER_NAME,
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.suppress_bind_attrs = true,
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},
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.probe = timbgpio_probe,
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};
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/*--------------------------------------------------------------------------*/
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builtin_platform_driver(timbgpio_platform_driver);
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