273 lines
6.8 KiB
C
273 lines
6.8 KiB
C
/*
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* Miscellaneous functions for IDT EB434 board
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*
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* Copyright 2004 IDT Inc. (rischelp@idt.com)
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* Copyright 2006 Phil Sutter <n0-1@freewrt.org>
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* Copyright 2007 Florian Fainelli <florian@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/spinlock.h>
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#include <linux/platform_device.h>
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#include <linux/gpio.h>
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#include <asm/mach-rc32434/rb.h>
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#include <asm/mach-rc32434/gpio.h>
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struct rb532_gpio_chip {
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struct gpio_chip chip;
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void __iomem *regbase;
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};
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struct mpmc_device dev3;
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static struct resource rb532_gpio_reg0_res[] = {
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{
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.name = "gpio_reg0",
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.start = REGBASE + GPIOBASE,
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.end = REGBASE + GPIOBASE + sizeof(struct rb532_gpio_reg) - 1,
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.flags = IORESOURCE_MEM,
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}
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};
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static struct resource rb532_dev3_ctl_res[] = {
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{
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.name = "dev3_ctl",
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.start = REGBASE + DEV3BASE,
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.end = REGBASE + DEV3BASE + sizeof(struct dev_reg) - 1,
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.flags = IORESOURCE_MEM,
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}
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};
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void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val)
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{
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unsigned long flags;
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unsigned data;
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unsigned i = 0;
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spin_lock_irqsave(&dev3.lock, flags);
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data = readl(IDT434_REG_BASE + reg_offs);
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for (i = 0; i != len; ++i) {
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if (val & (1 << i))
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data |= (1 << (i + bit));
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else
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data &= ~(1 << (i + bit));
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}
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writel(data, (IDT434_REG_BASE + reg_offs));
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spin_unlock_irqrestore(&dev3.lock, flags);
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}
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EXPORT_SYMBOL(set_434_reg);
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unsigned get_434_reg(unsigned reg_offs)
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{
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return readl(IDT434_REG_BASE + reg_offs);
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}
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EXPORT_SYMBOL(get_434_reg);
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void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
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{
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unsigned long flags;
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spin_lock_irqsave(&dev3.lock, flags);
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dev3.state = (dev3.state | or_mask) & ~nand_mask;
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writel(dev3.state, &dev3.base);
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spin_unlock_irqrestore(&dev3.lock, flags);
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}
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EXPORT_SYMBOL(set_latch_u5);
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unsigned char get_latch_u5(void)
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{
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return dev3.state;
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}
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EXPORT_SYMBOL(get_latch_u5);
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/* rb532_set_bit - sanely set a bit
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*
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* bitval: new value for the bit
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* offset: bit index in the 4 byte address range
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* ioaddr: 4 byte aligned address being altered
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*/
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static inline void rb532_set_bit(unsigned bitval,
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unsigned offset, void __iomem *ioaddr)
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{
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unsigned long flags;
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u32 val;
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bitval = !!bitval; /* map parameter to {0,1} */
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local_irq_save(flags);
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val = readl(ioaddr);
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val &= ~( ~bitval << offset ); /* unset bit if bitval == 0 */
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val |= ( bitval << offset ); /* set bit if bitval == 1 */
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writel(val, ioaddr);
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local_irq_restore(flags);
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}
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/* rb532_get_bit - read a bit
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*
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* returns the boolean state of the bit, which may be > 1
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*/
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static inline int rb532_get_bit(unsigned offset, void __iomem *ioaddr)
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{
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return (readl(ioaddr) & (1 << offset));
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}
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/*
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* Return GPIO level */
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static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct rb532_gpio_chip *gpch;
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gpch = container_of(chip, struct rb532_gpio_chip, chip);
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return rb532_get_bit(offset, gpch->regbase + GPIOD);
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}
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/*
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* Set output GPIO level
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*/
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static void rb532_gpio_set(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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struct rb532_gpio_chip *gpch;
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gpch = container_of(chip, struct rb532_gpio_chip, chip);
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rb532_set_bit(value, offset, gpch->regbase + GPIOD);
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}
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/*
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* Set GPIO direction to input
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*/
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static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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struct rb532_gpio_chip *gpch;
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gpch = container_of(chip, struct rb532_gpio_chip, chip);
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if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC))
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return 1; /* alternate function, GPIOCFG is ignored */
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rb532_set_bit(0, offset, gpch->regbase + GPIOCFG);
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return 0;
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}
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/*
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* Set GPIO direction to output
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*/
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static int rb532_gpio_direction_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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struct rb532_gpio_chip *gpch;
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gpch = container_of(chip, struct rb532_gpio_chip, chip);
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if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC))
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return 1; /* alternate function, GPIOCFG is ignored */
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/* set the initial output value */
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rb532_set_bit(value, offset, gpch->regbase + GPIOD);
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rb532_set_bit(1, offset, gpch->regbase + GPIOCFG);
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return 0;
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}
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static struct rb532_gpio_chip rb532_gpio_chip[] = {
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[0] = {
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.chip = {
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.label = "gpio0",
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.direction_input = rb532_gpio_direction_input,
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.direction_output = rb532_gpio_direction_output,
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.get = rb532_gpio_get,
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.set = rb532_gpio_set,
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.base = 0,
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.ngpio = 32,
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},
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},
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};
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/*
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* Set GPIO interrupt level
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*/
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void rb532_gpio_set_ilevel(int bit, unsigned gpio)
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{
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rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOILEVEL);
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}
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EXPORT_SYMBOL(rb532_gpio_set_ilevel);
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/*
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* Set GPIO interrupt status
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*/
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void rb532_gpio_set_istat(int bit, unsigned gpio)
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{
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rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOISTAT);
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}
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EXPORT_SYMBOL(rb532_gpio_set_istat);
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/*
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* Configure GPIO alternate function
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*/
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static void rb532_gpio_set_func(int bit, unsigned gpio)
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{
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rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOFUNC);
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}
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int __init rb532_gpio_init(void)
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{
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struct resource *r;
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r = rb532_gpio_reg0_res;
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rb532_gpio_chip->regbase = ioremap_nocache(r->start, r->end - r->start);
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if (!rb532_gpio_chip->regbase) {
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printk(KERN_ERR "rb532: cannot remap GPIO register 0\n");
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return -ENXIO;
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}
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/* Register our GPIO chip */
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gpiochip_add(&rb532_gpio_chip->chip);
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r = rb532_dev3_ctl_res;
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dev3.base = ioremap_nocache(r->start, r->end - r->start);
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if (!dev3.base) {
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printk(KERN_ERR "rb532: cannot remap device controller 3\n");
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return -ENXIO;
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}
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/* configure CF_GPIO_NUM as CFRDY IRQ source */
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rb532_gpio_set_func(0, CF_GPIO_NUM);
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rb532_gpio_direction_input(&rb532_gpio_chip->chip, CF_GPIO_NUM);
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rb532_gpio_set_ilevel(1, CF_GPIO_NUM);
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rb532_gpio_set_istat(0, CF_GPIO_NUM);
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return 0;
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}
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arch_initcall(rb532_gpio_init);
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