247 lines
7.1 KiB
C
247 lines
7.1 KiB
C
/*
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* linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
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*
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* Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef AACI_H
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#define AACI_H
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/*
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* Control and status register offsets
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* P39.
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*/
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#define AACI_CSCH1 0x000
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#define AACI_CSCH2 0x014
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#define AACI_CSCH3 0x028
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#define AACI_CSCH4 0x03c
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#define AACI_RXCR 0x000 /* 29 bits Control Rx FIFO */
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#define AACI_TXCR 0x004 /* 17 bits Control Tx FIFO */
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#define AACI_SR 0x008 /* 12 bits Status */
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#define AACI_ISR 0x00c /* 7 bits Int Status */
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#define AACI_IE 0x010 /* 7 bits Int Enable */
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/*
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* Other registers
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*/
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#define AACI_SL1RX 0x050
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#define AACI_SL1TX 0x054
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#define AACI_SL2RX 0x058
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#define AACI_SL2TX 0x05c
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#define AACI_SL12RX 0x060
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#define AACI_SL12TX 0x064
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#define AACI_SLFR 0x068 /* slot flags */
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#define AACI_SLISTAT 0x06c /* slot interrupt status */
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#define AACI_SLIEN 0x070 /* slot interrupt enable */
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#define AACI_INTCLR 0x074 /* interrupt clear */
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#define AACI_MAINCR 0x078 /* main control */
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#define AACI_RESET 0x07c /* reset control */
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#define AACI_SYNC 0x080 /* sync control */
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#define AACI_ALLINTS 0x084 /* all fifo interrupt status */
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#define AACI_MAINFR 0x088 /* main flag register */
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#define AACI_DR1 0x090 /* data read/written fifo 1 */
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#define AACI_DR2 0x0b0 /* data read/written fifo 2 */
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#define AACI_DR3 0x0d0 /* data read/written fifo 3 */
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#define AACI_DR4 0x0f0 /* data read/written fifo 4 */
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/*
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* transmit fifo control register. P48
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*/
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#define TXCR_FEN (1 << 16) /* fifo enable */
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#define TXCR_COMPACT (1 << 15) /* compact mode */
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#define TXCR_TSZ16 (0 << 13) /* 16 bits */
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#define TXCR_TSZ18 (1 << 13) /* 18 bits */
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#define TXCR_TSZ20 (2 << 13) /* 20 bits */
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#define TXCR_TSZ12 (3 << 13) /* 12 bits */
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#define TXCR_TX12 (1 << 12) /* transmits slot 12 */
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#define TXCR_TX11 (1 << 11) /* transmits slot 12 */
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#define TXCR_TX10 (1 << 10) /* transmits slot 12 */
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#define TXCR_TX9 (1 << 9) /* transmits slot 12 */
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#define TXCR_TX8 (1 << 8) /* transmits slot 12 */
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#define TXCR_TX7 (1 << 7) /* transmits slot 12 */
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#define TXCR_TX6 (1 << 6) /* transmits slot 12 */
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#define TXCR_TX5 (1 << 5) /* transmits slot 12 */
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#define TXCR_TX4 (1 << 4) /* transmits slot 12 */
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#define TXCR_TX3 (1 << 3) /* transmits slot 12 */
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#define TXCR_TX2 (1 << 2) /* transmits slot 12 */
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#define TXCR_TX1 (1 << 1) /* transmits slot 12 */
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#define TXCR_TXEN (1 << 0) /* transmit enable */
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/*
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* status register bits. P49
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*/
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#define SR_RXTOFE (1 << 11) /* rx timeout fifo empty */
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#define SR_TXTO (1 << 10) /* rx timeout fifo nonempty */
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#define SR_TXU (1 << 9) /* tx underrun */
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#define SR_RXO (1 << 8) /* rx overrun */
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#define SR_TXB (1 << 7) /* tx busy */
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#define SR_RXB (1 << 6) /* rx busy */
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#define SR_TXFF (1 << 5) /* tx fifo full */
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#define SR_RXFF (1 << 4) /* rx fifo full */
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#define SR_TXHE (1 << 3) /* tx fifo half empty */
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#define SR_RXHF (1 << 2) /* rx fifo half full */
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#define SR_TXFE (1 << 1) /* tx fifo empty */
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#define SR_RXFE (1 << 0) /* rx fifo empty */
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/*
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* interrupt status register bits.
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*/
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#define ISR_RXTOFEINTR (1 << 6) /* rx fifo empty */
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#define ISR_URINTR (1 << 5) /* tx underflow */
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#define ISR_ORINTR (1 << 4) /* rx overflow */
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#define ISR_RXINTR (1 << 3) /* rx fifo */
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#define ISR_TXINTR (1 << 2) /* tx fifo intr */
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#define ISR_RXTOINTR (1 << 1) /* tx timeout */
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#define ISR_TXCINTR (1 << 0) /* tx complete */
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/*
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* interrupt enable register bits.
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*/
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#define IE_RXTOIE (1 << 6)
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#define IE_URIE (1 << 5)
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#define IE_ORIE (1 << 4)
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#define IE_RXIE (1 << 3)
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#define IE_TXIE (1 << 2)
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#define IE_RXTIE (1 << 1)
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#define IE_TXCIE (1 << 0)
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/*
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* interrupt status. P51
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*/
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#define ISR_RXTOFE (1 << 6) /* rx timeout fifo empty */
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#define ISR_UR (1 << 5) /* tx fifo underrun */
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#define ISR_OR (1 << 4) /* rx fifo overrun */
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#define ISR_RX (1 << 3) /* rx interrupt status */
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#define ISR_TX (1 << 2) /* tx interrupt status */
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#define ISR_RXTO (1 << 1) /* rx timeout */
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#define ISR_TXC (1 << 0) /* tx complete */
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/*
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* interrupt enable. P52
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*/
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#define IE_RXTOFE (1 << 6) /* rx timeout fifo empty */
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#define IE_UR (1 << 5) /* tx fifo underrun */
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#define IE_OR (1 << 4) /* rx fifo overrun */
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#define IE_RX (1 << 3) /* rx interrupt status */
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#define IE_TX (1 << 2) /* tx interrupt status */
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#define IE_RXTO (1 << 1) /* rx timeout */
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#define IE_TXC (1 << 0) /* tx complete */
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/*
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* slot flag register bits. P56
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*/
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#define SLFR_RWIS (1 << 13) /* raw wake-up interrupt status */
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#define SLFR_RGPIOINTR (1 << 12) /* raw gpio interrupt */
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#define SLFR_12TXE (1 << 11) /* slot 12 tx empty */
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#define SLFR_12RXV (1 << 10) /* slot 12 rx valid */
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#define SLFR_2TXE (1 << 9) /* slot 2 tx empty */
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#define SLFR_2RXV (1 << 8) /* slot 2 rx valid */
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#define SLFR_1TXE (1 << 7) /* slot 1 tx empty */
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#define SLFR_1RXV (1 << 6) /* slot 1 rx valid */
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#define SLFR_12TXB (1 << 5) /* slot 12 tx busy */
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#define SLFR_12RXB (1 << 4) /* slot 12 rx busy */
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#define SLFR_2TXB (1 << 3) /* slot 2 tx busy */
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#define SLFR_2RXB (1 << 2) /* slot 2 rx busy */
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#define SLFR_1TXB (1 << 1) /* slot 1 tx busy */
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#define SLFR_1RXB (1 << 0) /* slot 1 rx busy */
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/*
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* Interrupt clear register.
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*/
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#define ICLR_RXTOFEC4 (1 << 12)
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#define ICLR_RXTOFEC3 (1 << 11)
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#define ICLR_RXTOFEC2 (1 << 10)
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#define ICLR_RXTOFEC1 (1 << 9)
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#define ICLR_TXUEC4 (1 << 8)
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#define ICLR_TXUEC3 (1 << 7)
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#define ICLR_TXUEC2 (1 << 6)
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#define ICLR_TXUEC1 (1 << 5)
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#define ICLR_RXOEC4 (1 << 4)
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#define ICLR_RXOEC3 (1 << 3)
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#define ICLR_RXOEC2 (1 << 2)
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#define ICLR_RXOEC1 (1 << 1)
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#define ICLR_WISC (1 << 0)
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/*
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* Main control register bits. P62
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*/
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#define MAINCR_SCRA(x) ((x) << 10) /* secondary codec reg access */
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#define MAINCR_DMAEN (1 << 9) /* dma enable */
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#define MAINCR_SL12TXEN (1 << 8) /* slot 12 transmit enable */
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#define MAINCR_SL12RXEN (1 << 7) /* slot 12 receive enable */
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#define MAINCR_SL2TXEN (1 << 6) /* slot 2 transmit enable */
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#define MAINCR_SL2RXEN (1 << 5) /* slot 2 receive enable */
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#define MAINCR_SL1TXEN (1 << 4) /* slot 1 transmit enable */
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#define MAINCR_SL1RXEN (1 << 3) /* slot 1 receive enable */
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#define MAINCR_LPM (1 << 2) /* low power mode */
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#define MAINCR_LOOPBK (1 << 1) /* loopback */
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#define MAINCR_IE (1 << 0) /* aaci interface enable */
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/*
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* Reset register bits. P65
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*/
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#define RESET_NRST (1 << 0)
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/*
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* Sync register bits. P65
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*/
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#define SYNC_FORCE (1 << 0)
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/*
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* Main flag register bits. P66
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*/
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#define MAINFR_TXB (1 << 1) /* transmit busy */
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#define MAINFR_RXB (1 << 0) /* receive busy */
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struct aaci_runtime {
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void __iomem *base;
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void __iomem *fifo;
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struct ac97_pcm *pcm;
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int pcm_open;
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u32 cr;
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struct snd_pcm_substream *substream;
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/*
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* PIO support
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*/
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void *start;
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void *end;
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void *ptr;
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int bytes;
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unsigned int period;
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unsigned int fifosz;
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};
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struct aaci {
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struct amba_device *dev;
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struct snd_card *card;
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void __iomem *base;
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unsigned int fifosize;
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/* AC'97 */
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struct semaphore ac97_sem;
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ac97_bus_t *ac97_bus;
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u32 maincr;
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spinlock_t lock;
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struct aaci_runtime playback;
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struct aaci_runtime capture;
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struct snd_pcm *pcm;
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};
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#define ACSTREAM_FRONT 0
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#define ACSTREAM_SURROUND 1
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#define ACSTREAM_LFE 2
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#endif
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