303 lines
7.8 KiB
C
303 lines
7.8 KiB
C
/* linux/arch/arm/plat-s3c24xx/cpu.c
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*
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* Copyright (c) 2004-2005 Simtec Electronics
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* http://www.simtec.co.uk/products/SWLINUX/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* Common code for S3C24XX machines
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/serial_core.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <mach/regs-clock.h>
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#include <asm/irq.h>
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#include <asm/cacheflush.h>
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#include <asm/system_info.h>
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#include <asm/system_misc.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <mach/regs-gpio.h>
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#include <plat/regs-serial.h>
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#include <plat/cpu.h>
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#include <plat/devs.h>
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#include <plat/clock.h>
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#include <plat/s3c2410.h>
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#include <plat/s3c2412.h>
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#include <plat/s3c2416.h>
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#include <plat/s3c244x.h>
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#include <plat/s3c2443.h>
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#include <plat/cpu-freq.h>
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#include <plat/pll.h>
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/* table of supported CPUs */
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static const char name_s3c2410[] = "S3C2410";
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static const char name_s3c2412[] = "S3C2412";
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static const char name_s3c2416[] = "S3C2416/S3C2450";
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static const char name_s3c2440[] = "S3C2440";
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static const char name_s3c2442[] = "S3C2442";
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static const char name_s3c2442b[] = "S3C2442B";
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static const char name_s3c2443[] = "S3C2443";
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static const char name_s3c2410a[] = "S3C2410A";
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static const char name_s3c2440a[] = "S3C2440A";
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static struct cpu_table cpu_ids[] __initdata = {
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{
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.idcode = 0x32410000,
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.idmask = 0xffffffff,
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.map_io = s3c2410_map_io,
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.init_clocks = s3c2410_init_clocks,
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.init_uarts = s3c2410_init_uarts,
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.init = s3c2410_init,
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.name = name_s3c2410
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},
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{
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.idcode = 0x32410002,
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.idmask = 0xffffffff,
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.map_io = s3c2410_map_io,
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.init_clocks = s3c2410_init_clocks,
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.init_uarts = s3c2410_init_uarts,
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.init = s3c2410a_init,
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.name = name_s3c2410a
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},
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{
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.idcode = 0x32440000,
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.idmask = 0xffffffff,
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.map_io = s3c2440_map_io,
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.init_clocks = s3c244x_init_clocks,
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.init_uarts = s3c244x_init_uarts,
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.init = s3c2440_init,
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.name = name_s3c2440
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},
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{
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.idcode = 0x32440001,
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.idmask = 0xffffffff,
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.map_io = s3c2440_map_io,
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.init_clocks = s3c244x_init_clocks,
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.init_uarts = s3c244x_init_uarts,
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.init = s3c2440_init,
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.name = name_s3c2440a
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},
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{
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.idcode = 0x32440aaa,
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.idmask = 0xffffffff,
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.map_io = s3c2442_map_io,
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.init_clocks = s3c244x_init_clocks,
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.init_uarts = s3c244x_init_uarts,
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.init = s3c2442_init,
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.name = name_s3c2442
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},
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{
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.idcode = 0x32440aab,
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.idmask = 0xffffffff,
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.map_io = s3c2442_map_io,
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.init_clocks = s3c244x_init_clocks,
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.init_uarts = s3c244x_init_uarts,
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.init = s3c2442_init,
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.name = name_s3c2442b
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},
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{
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.idcode = 0x32412001,
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.idmask = 0xffffffff,
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.map_io = s3c2412_map_io,
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.init_clocks = s3c2412_init_clocks,
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.init_uarts = s3c2412_init_uarts,
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.init = s3c2412_init,
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.name = name_s3c2412,
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},
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{ /* a newer version of the s3c2412 */
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.idcode = 0x32412003,
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.idmask = 0xffffffff,
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.map_io = s3c2412_map_io,
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.init_clocks = s3c2412_init_clocks,
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.init_uarts = s3c2412_init_uarts,
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.init = s3c2412_init,
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.name = name_s3c2412,
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},
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{ /* a strange version of the s3c2416 */
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.idcode = 0x32450003,
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.idmask = 0xffffffff,
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.map_io = s3c2416_map_io,
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.init_clocks = s3c2416_init_clocks,
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.init_uarts = s3c2416_init_uarts,
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.init = s3c2416_init,
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.name = name_s3c2416,
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},
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{
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.idcode = 0x32443001,
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.idmask = 0xffffffff,
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.map_io = s3c2443_map_io,
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.init_clocks = s3c2443_init_clocks,
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.init_uarts = s3c2443_init_uarts,
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.init = s3c2443_init,
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.name = name_s3c2443,
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},
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};
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/* minimal IO mapping */
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static struct map_desc s3c_iodesc[] __initdata = {
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IODESC_ENT(GPIO),
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IODESC_ENT(IRQ),
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IODESC_ENT(MEMCTRL),
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IODESC_ENT(UART)
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};
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/* read cpu identificaiton code */
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static unsigned long s3c24xx_read_idcode_v5(void)
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{
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#if defined(CONFIG_CPU_S3C2416)
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/* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */
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u32 gs = __raw_readl(S3C24XX_GSTATUS1);
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/* test for s3c2416 or similar device */
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if ((gs >> 16) == 0x3245)
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return gs;
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#endif
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#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
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return __raw_readl(S3C2412_GSTATUS1);
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#else
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return 1UL; /* don't look like an 2400 */
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#endif
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}
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static unsigned long s3c24xx_read_idcode_v4(void)
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{
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return __raw_readl(S3C2410_GSTATUS1);
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}
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static void s3c24xx_default_idle(void)
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{
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unsigned long tmp;
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int i;
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/* idle the system by using the idle mode which will wait for an
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* interrupt to happen before restarting the system.
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*/
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/* Warning: going into idle state upsets jtag scanning */
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__raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
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S3C2410_CLKCON);
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/* the samsung port seems to do a loop and then unset idle.. */
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for (i = 0; i < 50; i++)
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tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
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/* this bit is not cleared on re-start... */
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__raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
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S3C2410_CLKCON);
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}
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void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
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{
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arm_pm_idle = s3c24xx_default_idle;
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/* initialise the io descriptors we need for initialisation */
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iotable_init(mach_desc, size);
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iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
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if (cpu_architecture() >= CPU_ARCH_ARMv5) {
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samsung_cpu_id = s3c24xx_read_idcode_v5();
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} else {
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samsung_cpu_id = s3c24xx_read_idcode_v4();
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}
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s3c24xx_init_cpu();
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s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
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}
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/* Serial port registrations */
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static struct resource s3c2410_uart0_resource[] = {
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[0] = DEFINE_RES_MEM(S3C2410_PA_UART0, SZ_16K),
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[1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX0, \
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IRQ_S3CUART_ERR0 - IRQ_S3CUART_RX0 + 1, \
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NULL, IORESOURCE_IRQ)
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};
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static struct resource s3c2410_uart1_resource[] = {
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[0] = DEFINE_RES_MEM(S3C2410_PA_UART1, SZ_16K),
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[1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX1, \
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IRQ_S3CUART_ERR1 - IRQ_S3CUART_RX1 + 1, \
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NULL, IORESOURCE_IRQ)
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};
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static struct resource s3c2410_uart2_resource[] = {
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[0] = DEFINE_RES_MEM(S3C2410_PA_UART2, SZ_16K),
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[1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX2, \
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IRQ_S3CUART_ERR2 - IRQ_S3CUART_RX2 + 1, \
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NULL, IORESOURCE_IRQ)
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};
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static struct resource s3c2410_uart3_resource[] = {
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[0] = DEFINE_RES_MEM(S3C2443_PA_UART3, SZ_16K),
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[1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX3, \
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IRQ_S3CUART_ERR3 - IRQ_S3CUART_RX3 + 1, \
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NULL, IORESOURCE_IRQ)
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};
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struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
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[0] = {
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.resources = s3c2410_uart0_resource,
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.nr_resources = ARRAY_SIZE(s3c2410_uart0_resource),
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},
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[1] = {
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.resources = s3c2410_uart1_resource,
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.nr_resources = ARRAY_SIZE(s3c2410_uart1_resource),
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},
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[2] = {
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.resources = s3c2410_uart2_resource,
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.nr_resources = ARRAY_SIZE(s3c2410_uart2_resource),
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},
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[3] = {
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.resources = s3c2410_uart3_resource,
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.nr_resources = ARRAY_SIZE(s3c2410_uart3_resource),
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},
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};
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/* initialise all the clocks */
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void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk,
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unsigned long hclk,
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unsigned long pclk)
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{
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clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON),
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clk_xtal.rate);
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clk_mpll.rate = fclk;
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clk_h.rate = hclk;
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clk_p.rate = pclk;
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clk_f.rate = fclk;
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}
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