4ea69b2fd6
For multi-function programs, loading the address of a callee function to a register requires emitting instructions whose count varies from one to five depending on the nature of the address. Since we come to know of the callee's address only before the extra pass, the number of instructions required to load this address may vary from what was previously generated. This can make the JITed image grow or shrink. To avoid this, we should generate a constant five-instruction when loading function addresses by padding the optimized load sequence with NOPs. Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> |
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| .. | ||
| Makefile | ||
| bpf_jit.h | ||
| bpf_jit32.h | ||
| bpf_jit64.h | ||
| bpf_jit_asm.S | ||
| bpf_jit_comp.c | ||
| bpf_jit_comp64.c | ||