2937 lines
101 KiB
C
2937 lines
101 KiB
C
/*
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Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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* Neither the name of Trident Microsystems nor Hauppauge Computer Works
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nor the names of its contributors may be used to endorse or promote
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products derived from this software without specific prior written
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permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* \file $Id: drx_driver.h,v 1.84 2010/01/14 22:47:50 dingtao Exp $
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*
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* \brief DRX driver API
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*
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*/
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#ifndef __DRXDRIVER_H__
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#define __DRXDRIVER_H__
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#include <linux/kernel.h>
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/*-------------------------------------------------------------------------
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INCLUDES
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-------------------------------------------------------------------------*/
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enum drx_status {
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DRX_STS_READY = 3, /**< device/service is ready */
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DRX_STS_BUSY = 2, /**< device/service is busy */
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DRX_STS_OK = 1, /**< everything is OK */
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DRX_STS_INVALID_ARG = -1,
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/**< invalid arguments */
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DRX_STS_ERROR = -2, /**< general error */
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DRX_STS_FUNC_NOT_AVAILABLE = -3
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/**< unavailable functionality */
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};
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/*
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* This structure contains the I2C address, the device ID and a user_data pointer.
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* The user_data pointer can be used for application specific purposes.
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*/
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struct i2c_device_addr {
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u16 i2c_addr; /* The I2C address of the device. */
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u16 i2c_dev_id; /* The device identifier. */
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void *user_data; /* User data pointer */
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};
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/**
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* \def IS_I2C_10BIT( addr )
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* \brief Determine if I2C address 'addr' is a 10 bits address or not.
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* \param addr The I2C address.
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* \return int.
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* \retval 0 if address is not a 10 bits I2C address.
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* \retval 1 if address is a 10 bits I2C address.
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*/
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#define IS_I2C_10BIT(addr) \
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(((addr) & 0xF8) == 0xF0)
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/*------------------------------------------------------------------------------
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Exported FUNCTIONS
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------------------------------------------------------------------------------*/
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/**
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* \fn drxbsp_i2c_init()
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* \brief Initialize I2C communication module.
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* \return int Return status.
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* \retval DRX_STS_OK Initialization successful.
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* \retval DRX_STS_ERROR Initialization failed.
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*/
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int drxbsp_i2c_init(void);
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/**
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* \fn drxbsp_i2c_term()
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* \brief Terminate I2C communication module.
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* \return int Return status.
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* \retval DRX_STS_OK Termination successful.
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* \retval DRX_STS_ERROR Termination failed.
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*/
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int drxbsp_i2c_term(void);
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/**
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* \fn int drxbsp_i2c_write_read( struct i2c_device_addr *w_dev_addr,
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* u16 w_count,
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* u8 * wData,
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* struct i2c_device_addr *r_dev_addr,
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* u16 r_count,
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* u8 * r_data)
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* \brief Read and/or write count bytes from I2C bus, store them in data[].
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* \param w_dev_addr The device i2c address and the device ID to write to
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* \param w_count The number of bytes to write
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* \param wData The array to write the data to
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* \param r_dev_addr The device i2c address and the device ID to read from
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* \param r_count The number of bytes to read
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* \param r_data The array to read the data from
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* \return int Return status.
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* \retval DRX_STS_OK Succes.
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* \retval DRX_STS_ERROR Failure.
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* \retval DRX_STS_INVALID_ARG Parameter 'wcount' is not zero but parameter
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* 'wdata' contains NULL.
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* Idem for 'rcount' and 'rdata'.
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* Both w_dev_addr and r_dev_addr are NULL.
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*
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* This function must implement an atomic write and/or read action on the I2C bus
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* No other process may use the I2C bus when this function is executing.
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* The critical section of this function runs from and including the I2C
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* write, up to and including the I2C read action.
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*
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* The device ID can be useful if several devices share an I2C address.
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* It can be used to control a "switch" on the I2C bus to the correct device.
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*/
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int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr,
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u16 w_count,
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u8 *wData,
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struct i2c_device_addr *r_dev_addr,
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u16 r_count, u8 *r_data);
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/**
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* \fn drxbsp_i2c_error_text()
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* \brief Returns a human readable error.
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* Counter part of numerical drx_i2c_error_g.
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*
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* \return char* Pointer to human readable error text.
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*/
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char *drxbsp_i2c_error_text(void);
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/**
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* \var drx_i2c_error_g;
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* \brief I2C specific error codes, platform dependent.
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*/
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extern int drx_i2c_error_g;
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#define TUNER_MODE_SUB0 0x0001 /* for sub-mode (e.g. RF-AGC setting) */
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#define TUNER_MODE_SUB1 0x0002 /* for sub-mode (e.g. RF-AGC setting) */
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#define TUNER_MODE_SUB2 0x0004 /* for sub-mode (e.g. RF-AGC setting) */
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#define TUNER_MODE_SUB3 0x0008 /* for sub-mode (e.g. RF-AGC setting) */
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#define TUNER_MODE_SUB4 0x0010 /* for sub-mode (e.g. RF-AGC setting) */
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#define TUNER_MODE_SUB5 0x0020 /* for sub-mode (e.g. RF-AGC setting) */
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#define TUNER_MODE_SUB6 0x0040 /* for sub-mode (e.g. RF-AGC setting) */
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#define TUNER_MODE_SUB7 0x0080 /* for sub-mode (e.g. RF-AGC setting) */
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#define TUNER_MODE_DIGITAL 0x0100 /* for digital channel (e.g. DVB-T) */
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#define TUNER_MODE_ANALOG 0x0200 /* for analog channel (e.g. PAL) */
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#define TUNER_MODE_SWITCH 0x0400 /* during channel switch & scanning */
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#define TUNER_MODE_LOCK 0x0800 /* after tuner has locked */
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#define TUNER_MODE_6MHZ 0x1000 /* for 6MHz bandwidth channels */
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#define TUNER_MODE_7MHZ 0x2000 /* for 7MHz bandwidth channels */
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#define TUNER_MODE_8MHZ 0x4000 /* for 8MHz bandwidth channels */
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#define TUNER_MODE_SUB_MAX 8
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#define TUNER_MODE_SUBALL (TUNER_MODE_SUB0 | TUNER_MODE_SUB1 | \
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TUNER_MODE_SUB2 | TUNER_MODE_SUB3 | \
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TUNER_MODE_SUB4 | TUNER_MODE_SUB5 | \
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TUNER_MODE_SUB6 | TUNER_MODE_SUB7)
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enum tuner_lock_status {
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TUNER_LOCKED,
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TUNER_NOT_LOCKED
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};
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struct tuner_common {
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char *name; /* Tuner brand & type name */
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s32 min_freq_rf; /* Lowest RF input frequency, in kHz */
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s32 max_freq_rf; /* Highest RF input frequency, in kHz */
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u8 sub_mode; /* Index to sub-mode in use */
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char ***sub_modeDescriptions; /* Pointer to description of sub-modes */
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u8 sub_modes; /* Number of available sub-modes */
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/* The following fields will be either 0, NULL or false and do not need
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initialisation */
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void *self_check; /* gives proof of initialization */
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bool programmed; /* only valid if self_check is OK */
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s32 r_ffrequency; /* only valid if programmed */
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s32 i_ffrequency; /* only valid if programmed */
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void *myUser_data; /* pointer to associated demod instance */
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u16 my_capabilities; /* value for storing application flags */
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};
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struct tuner_instance;
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typedef int(*tuner_open_func_t) (struct tuner_instance *tuner);
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typedef int(*tuner_close_func_t) (struct tuner_instance *tuner);
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typedef int(*tuner_set_frequency_func_t) (struct tuner_instance *tuner,
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u32 mode,
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s32
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frequency);
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typedef int(*tuner_get_frequency_func_t) (struct tuner_instance *tuner,
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u32 mode,
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s32 *
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r_ffrequency,
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s32 *
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i_ffrequency);
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typedef int(*tuner_lock_status_func_t) (struct tuner_instance *tuner,
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enum tuner_lock_status *
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lock_stat);
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typedef int(*tune_ri2c_write_read_func_t) (struct tuner_instance *tuner,
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struct i2c_device_addr *
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w_dev_addr, u16 w_count,
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u8 *wData,
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struct i2c_device_addr *
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r_dev_addr, u16 r_count,
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u8 *r_data);
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struct tuner_ops {
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tuner_open_func_t open_func;
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tuner_close_func_t close_func;
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tuner_set_frequency_func_t set_frequency_func;
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tuner_get_frequency_func_t get_frequency_func;
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tuner_lock_status_func_t lock_statusFunc;
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tune_ri2c_write_read_func_t i2c_write_read_func;
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};
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struct tuner_instance {
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struct i2c_device_addr my_i2c_dev_addr;
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struct tuner_common *my_common_attr;
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void *my_ext_attr;
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struct tuner_ops *my_funct;
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};
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int drxbsp_tuner_open(struct tuner_instance *tuner);
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int drxbsp_tuner_close(struct tuner_instance *tuner);
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int drxbsp_tuner_set_frequency(struct tuner_instance *tuner,
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u32 mode,
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s32 frequency);
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int drxbsp_tuner_get_frequency(struct tuner_instance *tuner,
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u32 mode,
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s32 *r_ffrequency,
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s32 *i_ffrequency);
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int drxbsp_tuner_lock_status(struct tuner_instance *tuner,
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enum tuner_lock_status *lock_stat);
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int drxbsp_tuner_default_i2c_write_read(struct tuner_instance *tuner,
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struct i2c_device_addr *w_dev_addr,
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u16 w_count,
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u8 *wData,
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struct i2c_device_addr *r_dev_addr,
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u16 r_count, u8 *r_data);
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int drxbsp_hst_init(void);
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int drxbsp_hst_term(void);
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void *drxbsp_hst_memcpy(void *to, void *from, u32 n);
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int drxbsp_hst_memcmp(void *s1, void *s2, u32 n);
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u32 drxbsp_hst_clock(void);
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int drxbsp_hst_sleep(u32 n);
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/**************
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*
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* This section configures the DRX Data Access Protocols (DAPs).
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*
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**************/
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/**
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* \def DRXDAP_SINGLE_MASTER
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* \brief Enable I2C single or I2C multimaster mode on host.
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*
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* Set to 1 to enable single master mode
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* Set to 0 to enable multi master mode
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*
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* The actual DAP implementation may be restricted to only one of the modes.
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* A compiler warning or error will be generated if the DAP implementation
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* overides or cannot handle the mode defined below.
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*
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*/
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#ifndef DRXDAP_SINGLE_MASTER
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#define DRXDAP_SINGLE_MASTER 0
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#endif
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/**
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* \def DRXDAP_MAX_WCHUNKSIZE
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* \brief Defines maximum chunksize of an i2c write action by host.
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*
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* This indicates the maximum size of data the I2C device driver is able to
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* write at a time. This includes I2C device address and register addressing.
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*
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* This maximum size may be restricted by the actual DAP implementation.
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* A compiler warning or error will be generated if the DAP implementation
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* overides or cannot handle the chunksize defined below.
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*
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* Beware that the DAP uses DRXDAP_MAX_WCHUNKSIZE to create a temporary data
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* buffer. Do not undefine or choose too large, unless your system is able to
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* handle a stack buffer of that size.
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*
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*/
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#ifndef DRXDAP_MAX_WCHUNKSIZE
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#define DRXDAP_MAX_WCHUNKSIZE 60
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#endif
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/**
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* \def DRXDAP_MAX_RCHUNKSIZE
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* \brief Defines maximum chunksize of an i2c read action by host.
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*
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* This indicates the maximum size of data the I2C device driver is able to read
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* at a time. Minimum value is 2. Also, the read chunk size must be even.
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*
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* This maximum size may be restricted by the actual DAP implementation.
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* A compiler warning or error will be generated if the DAP implementation
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* overides or cannot handle the chunksize defined below.
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*
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*/
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#ifndef DRXDAP_MAX_RCHUNKSIZE
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#define DRXDAP_MAX_RCHUNKSIZE 60
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#endif
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/**************
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*
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* This section describes drxdriver defines.
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*
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**************/
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/**
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* \def DRX_UNKNOWN
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* \brief Generic UNKNOWN value for DRX enumerated types.
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*
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* Used to indicate that the parameter value is unknown or not yet initalized.
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*/
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#ifndef DRX_UNKNOWN
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#define DRX_UNKNOWN (254)
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#endif
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/**
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* \def DRX_AUTO
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* \brief Generic AUTO value for DRX enumerated types.
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*
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* Used to instruct the driver to automatically determine the value of the
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* parameter.
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*/
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#ifndef DRX_AUTO
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#define DRX_AUTO (255)
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#endif
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/**************
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*
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* This section describes flag definitions for the device capbilities.
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*
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**************/
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/**
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* \brief LNA capability flag
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*
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* Device has a Low Noise Amplifier
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*
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*/
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#define DRX_CAPABILITY_HAS_LNA (1UL << 0)
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/**
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* \brief OOB-RX capability flag
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*
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* Device has OOB-RX
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*
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*/
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#define DRX_CAPABILITY_HAS_OOBRX (1UL << 1)
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/**
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* \brief ATV capability flag
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*
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* Device has ATV
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*
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*/
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#define DRX_CAPABILITY_HAS_ATV (1UL << 2)
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/**
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* \brief DVB-T capability flag
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*
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* Device has DVB-T
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*
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*/
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#define DRX_CAPABILITY_HAS_DVBT (1UL << 3)
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/**
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* \brief ITU-B capability flag
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*
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* Device has ITU-B
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*
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*/
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#define DRX_CAPABILITY_HAS_ITUB (1UL << 4)
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/**
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* \brief Audio capability flag
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*
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* Device has Audio
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*
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*/
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#define DRX_CAPABILITY_HAS_AUD (1UL << 5)
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/**
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* \brief SAW switch capability flag
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*
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* Device has SAW switch
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*
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*/
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#define DRX_CAPABILITY_HAS_SAWSW (1UL << 6)
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/**
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* \brief GPIO1 capability flag
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*
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* Device has GPIO1
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*
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*/
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#define DRX_CAPABILITY_HAS_GPIO1 (1UL << 7)
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/**
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* \brief GPIO2 capability flag
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*
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* Device has GPIO2
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*
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*/
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#define DRX_CAPABILITY_HAS_GPIO2 (1UL << 8)
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/**
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* \brief IRQN capability flag
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*
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* Device has IRQN
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*
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*/
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#define DRX_CAPABILITY_HAS_IRQN (1UL << 9)
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/**
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* \brief 8VSB capability flag
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*
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* Device has 8VSB
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*
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*/
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#define DRX_CAPABILITY_HAS_8VSB (1UL << 10)
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/**
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* \brief SMA-TX capability flag
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*
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* Device has SMATX
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*
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*/
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#define DRX_CAPABILITY_HAS_SMATX (1UL << 11)
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/**
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* \brief SMA-RX capability flag
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*
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* Device has SMARX
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*
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*/
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#define DRX_CAPABILITY_HAS_SMARX (1UL << 12)
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/**
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* \brief ITU-A/C capability flag
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*
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* Device has ITU-A/C
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*
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*/
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#define DRX_CAPABILITY_HAS_ITUAC (1UL << 13)
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/*-------------------------------------------------------------------------
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MACROS
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-------------------------------------------------------------------------*/
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/* Macros to stringify the version number */
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#define DRX_VERSIONSTRING(MAJOR, MINOR, PATCH) \
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DRX_VERSIONSTRING_HELP(MAJOR)"." \
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DRX_VERSIONSTRING_HELP(MINOR)"." \
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DRX_VERSIONSTRING_HELP(PATCH)
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#define DRX_VERSIONSTRING_HELP(NUM) #NUM
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/**
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* \brief Macro to create byte array elements from 16 bit integers.
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* This macro is used to create byte arrays for block writes.
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* Block writes speed up I2C traffic between host and demod.
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* The macro takes care of the required byte order in a 16 bits word.
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* x->lowbyte(x), highbyte(x)
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*/
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#define DRX_16TO8(x) ((u8) (((u16)x) & 0xFF)), \
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((u8)((((u16)x)>>8)&0xFF))
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/**
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* \brief Macro to sign extend signed 9 bit value to signed 16 bit value
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*/
|
|
#define DRX_S9TOS16(x) ((((u16)x)&0x100) ? ((s16)((u16)(x)|0xFF00)) : (x))
|
|
|
|
/**
|
|
* \brief Macro to sign extend signed 9 bit value to signed 16 bit value
|
|
*/
|
|
#define DRX_S24TODRXFREQ(x) ((( (u32) x) & 0x00800000UL) ? \
|
|
((s32) \
|
|
(((u32) x) | 0xFF000000) ) : \
|
|
((s32) x))
|
|
|
|
/**
|
|
* \brief Macro to convert 16 bit register value to a s32
|
|
*/
|
|
#define DRX_U16TODRXFREQ(x) ((x & 0x8000) ? \
|
|
((s32) \
|
|
(((u32) x) | 0xFFFF0000) ) : \
|
|
((s32) x))
|
|
|
|
/*-------------------------------------------------------------------------
|
|
ENUM
|
|
-------------------------------------------------------------------------*/
|
|
|
|
/**
|
|
* \enum enum drx_standard
|
|
* \brief Modulation standards.
|
|
*/
|
|
enum drx_standard {
|
|
DRX_STANDARD_DVBT = 0, /**< Terrestrial DVB-T. */
|
|
DRX_STANDARD_8VSB, /**< Terrestrial 8VSB. */
|
|
DRX_STANDARD_NTSC, /**< Terrestrial\Cable analog NTSC. */
|
|
DRX_STANDARD_PAL_SECAM_BG,
|
|
/**< Terrestrial analog PAL/SECAM B/G */
|
|
DRX_STANDARD_PAL_SECAM_DK,
|
|
/**< Terrestrial analog PAL/SECAM D/K */
|
|
DRX_STANDARD_PAL_SECAM_I,
|
|
/**< Terrestrial analog PAL/SECAM I */
|
|
DRX_STANDARD_PAL_SECAM_L,
|
|
/**< Terrestrial analog PAL/SECAM L
|
|
with negative modulation */
|
|
DRX_STANDARD_PAL_SECAM_LP,
|
|
/**< Terrestrial analog PAL/SECAM L
|
|
with positive modulation */
|
|
DRX_STANDARD_ITU_A, /**< Cable ITU ANNEX A. */
|
|
DRX_STANDARD_ITU_B, /**< Cable ITU ANNEX B. */
|
|
DRX_STANDARD_ITU_C, /**< Cable ITU ANNEX C. */
|
|
DRX_STANDARD_ITU_D, /**< Cable ITU ANNEX D. */
|
|
DRX_STANDARD_FM, /**< Terrestrial\Cable FM radio */
|
|
DRX_STANDARD_DTMB, /**< Terrestrial DTMB standard (China)*/
|
|
DRX_STANDARD_UNKNOWN = DRX_UNKNOWN,
|
|
/**< Standard unknown. */
|
|
DRX_STANDARD_AUTO = DRX_AUTO
|
|
/**< Autodetect standard. */
|
|
};
|
|
|
|
/**
|
|
* \enum enum drx_standard
|
|
* \brief Modulation sub-standards.
|
|
*/
|
|
enum drx_substandard {
|
|
DRX_SUBSTANDARD_MAIN = 0, /**< Main subvariant of standard */
|
|
DRX_SUBSTANDARD_ATV_BG_SCANDINAVIA,
|
|
DRX_SUBSTANDARD_ATV_DK_POLAND,
|
|
DRX_SUBSTANDARD_ATV_DK_CHINA,
|
|
DRX_SUBSTANDARD_UNKNOWN = DRX_UNKNOWN,
|
|
/**< Sub-standard unknown. */
|
|
DRX_SUBSTANDARD_AUTO = DRX_AUTO
|
|
/**< Auto (default) sub-standard */
|
|
};
|
|
|
|
/**
|
|
* \enum enum drx_bandwidth
|
|
* \brief Channel bandwidth or channel spacing.
|
|
*/
|
|
enum drx_bandwidth {
|
|
DRX_BANDWIDTH_8MHZ = 0, /**< Bandwidth 8 MHz. */
|
|
DRX_BANDWIDTH_7MHZ, /**< Bandwidth 7 MHz. */
|
|
DRX_BANDWIDTH_6MHZ, /**< Bandwidth 6 MHz. */
|
|
DRX_BANDWIDTH_UNKNOWN = DRX_UNKNOWN,
|
|
/**< Bandwidth unknown. */
|
|
DRX_BANDWIDTH_AUTO = DRX_AUTO
|
|
/**< Auto Set Bandwidth */
|
|
};
|
|
|
|
/**
|
|
* \enum enum drx_mirror
|
|
* \brief Indicate if channel spectrum is mirrored or not.
|
|
*/
|
|
enum drx_mirror {
|
|
DRX_MIRROR_NO = 0, /**< Spectrum is not mirrored. */
|
|
DRX_MIRROR_YES, /**< Spectrum is mirrored. */
|
|
DRX_MIRROR_UNKNOWN = DRX_UNKNOWN,
|
|
/**< Unknown if spectrum is mirrored. */
|
|
DRX_MIRROR_AUTO = DRX_AUTO
|
|
/**< Autodetect if spectrum is mirrored. */
|
|
};
|
|
|
|
/**
|
|
* \enum enum drx_modulation
|
|
* \brief Constellation type of the channel.
|
|
*/
|
|
enum drx_modulation {
|
|
DRX_CONSTELLATION_BPSK = 0, /**< Modulation is BPSK. */
|
|
DRX_CONSTELLATION_QPSK, /**< Constellation is QPSK. */
|
|
DRX_CONSTELLATION_PSK8, /**< Constellation is PSK8. */
|
|
DRX_CONSTELLATION_QAM16, /**< Constellation is QAM16. */
|
|
DRX_CONSTELLATION_QAM32, /**< Constellation is QAM32. */
|
|
DRX_CONSTELLATION_QAM64, /**< Constellation is QAM64. */
|
|
DRX_CONSTELLATION_QAM128, /**< Constellation is QAM128. */
|
|
DRX_CONSTELLATION_QAM256, /**< Constellation is QAM256. */
|
|
DRX_CONSTELLATION_QAM512, /**< Constellation is QAM512. */
|
|
DRX_CONSTELLATION_QAM1024, /**< Constellation is QAM1024. */
|
|
DRX_CONSTELLATION_QPSK_NR, /**< Constellation is QPSK_NR */
|
|
DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN,
|
|
/**< Constellation unknown. */
|
|
DRX_CONSTELLATION_AUTO = DRX_AUTO
|
|
/**< Autodetect constellation. */
|
|
};
|
|
|
|
/**
|
|
* \enum enum drx_hierarchy
|
|
* \brief Hierarchy of the channel.
|
|
*/
|
|
enum drx_hierarchy {
|
|
DRX_HIERARCHY_NONE = 0, /**< None hierarchical channel. */
|
|
DRX_HIERARCHY_ALPHA1, /**< Hierarchical channel, alpha=1. */
|
|
DRX_HIERARCHY_ALPHA2, /**< Hierarchical channel, alpha=2. */
|
|
DRX_HIERARCHY_ALPHA4, /**< Hierarchical channel, alpha=4. */
|
|
DRX_HIERARCHY_UNKNOWN = DRX_UNKNOWN,
|
|
/**< Hierarchy unknown. */
|
|
DRX_HIERARCHY_AUTO = DRX_AUTO
|
|
/**< Autodetect hierarchy. */
|
|
};
|
|
|
|
/**
|
|
* \enum enum drx_priority
|
|
* \brief Channel priority in case of hierarchical transmission.
|
|
*/
|
|
enum drx_priority {
|
|
DRX_PRIORITY_LOW = 0, /**< Low priority channel. */
|
|
DRX_PRIORITY_HIGH, /**< High priority channel. */
|
|
DRX_PRIORITY_UNKNOWN = DRX_UNKNOWN
|
|
/**< Priority unknown. */
|
|
};
|
|
|
|
/**
|
|
* \enum enum drx_coderate
|
|
* \brief Channel priority in case of hierarchical transmission.
|
|
*/
|
|
enum drx_coderate {
|
|
DRX_CODERATE_1DIV2 = 0, /**< Code rate 1/2nd. */
|
|
DRX_CODERATE_2DIV3, /**< Code rate 2/3nd. */
|
|
DRX_CODERATE_3DIV4, /**< Code rate 3/4nd. */
|
|
DRX_CODERATE_5DIV6, /**< Code rate 5/6nd. */
|
|
DRX_CODERATE_7DIV8, /**< Code rate 7/8nd. */
|
|
DRX_CODERATE_UNKNOWN = DRX_UNKNOWN,
|
|
/**< Code rate unknown. */
|
|
DRX_CODERATE_AUTO = DRX_AUTO
|
|
/**< Autodetect code rate. */
|
|
};
|
|
|
|
/**
|
|
* \enum enum drx_guard
|
|
* \brief Guard interval of a channel.
|
|
*/
|
|
enum drx_guard {
|
|
DRX_GUARD_1DIV32 = 0, /**< Guard interval 1/32nd. */
|
|
DRX_GUARD_1DIV16, /**< Guard interval 1/16th. */
|
|
DRX_GUARD_1DIV8, /**< Guard interval 1/8th. */
|
|
DRX_GUARD_1DIV4, /**< Guard interval 1/4th. */
|
|
DRX_GUARD_UNKNOWN = DRX_UNKNOWN,
|
|
/**< Guard interval unknown. */
|
|
DRX_GUARD_AUTO = DRX_AUTO
|
|
/**< Autodetect guard interval. */
|
|
};
|
|
|
|
/**
|
|
* \enum enum drx_fft_mode
|
|
* \brief FFT mode.
|
|
*/
|
|
enum drx_fft_mode {
|
|
DRX_FFTMODE_2K = 0, /**< 2K FFT mode. */
|
|
DRX_FFTMODE_4K, /**< 4K FFT mode. */
|
|
DRX_FFTMODE_8K, /**< 8K FFT mode. */
|
|
DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN,
|
|
/**< FFT mode unknown. */
|
|
DRX_FFTMODE_AUTO = DRX_AUTO
|
|
/**< Autodetect FFT mode. */
|
|
};
|
|
|
|
/**
|
|
* \enum enum drx_classification
|
|
* \brief Channel classification.
|
|
*/
|
|
enum drx_classification {
|
|
DRX_CLASSIFICATION_GAUSS = 0, /**< Gaussion noise. */
|
|
DRX_CLASSIFICATION_HVY_GAUSS, /**< Heavy Gaussion noise. */
|
|
DRX_CLASSIFICATION_COCHANNEL, /**< Co-channel. */
|
|
DRX_CLASSIFICATION_STATIC, /**< Static echo. */
|
|
DRX_CLASSIFICATION_MOVING, /**< Moving echo. */
|
|
DRX_CLASSIFICATION_ZERODB, /**< Zero dB echo. */
|
|
DRX_CLASSIFICATION_UNKNOWN = DRX_UNKNOWN,
|
|
/**< Unknown classification */
|
|
DRX_CLASSIFICATION_AUTO = DRX_AUTO
|
|
/**< Autodetect classification. */
|
|
};
|
|
|
|
/**
|
|
* /enum enum drx_interleave_mode
|
|
* /brief Interleave modes
|
|
*/
|
|
enum drx_interleave_mode {
|
|
DRX_INTERLEAVEMODE_I128_J1 = 0,
|
|
DRX_INTERLEAVEMODE_I128_J1_V2,
|
|
DRX_INTERLEAVEMODE_I128_J2,
|
|
DRX_INTERLEAVEMODE_I64_J2,
|
|
DRX_INTERLEAVEMODE_I128_J3,
|
|
DRX_INTERLEAVEMODE_I32_J4,
|
|
DRX_INTERLEAVEMODE_I128_J4,
|
|
DRX_INTERLEAVEMODE_I16_J8,
|
|
DRX_INTERLEAVEMODE_I128_J5,
|
|
DRX_INTERLEAVEMODE_I8_J16,
|
|
DRX_INTERLEAVEMODE_I128_J6,
|
|
DRX_INTERLEAVEMODE_RESERVED_11,
|
|
DRX_INTERLEAVEMODE_I128_J7,
|
|
DRX_INTERLEAVEMODE_RESERVED_13,
|
|
DRX_INTERLEAVEMODE_I128_J8,
|
|
DRX_INTERLEAVEMODE_RESERVED_15,
|
|
DRX_INTERLEAVEMODE_I12_J17,
|
|
DRX_INTERLEAVEMODE_I5_J4,
|
|
DRX_INTERLEAVEMODE_B52_M240,
|
|
DRX_INTERLEAVEMODE_B52_M720,
|
|
DRX_INTERLEAVEMODE_B52_M48,
|
|
DRX_INTERLEAVEMODE_B52_M0,
|
|
DRX_INTERLEAVEMODE_UNKNOWN = DRX_UNKNOWN,
|
|
/**< Unknown interleave mode */
|
|
DRX_INTERLEAVEMODE_AUTO = DRX_AUTO
|
|
/**< Autodetect interleave mode */
|
|
};
|
|
|
|
/**
|
|
* \enum enum drx_carrier_mode
|
|
* \brief Channel Carrier Mode.
|
|
*/
|
|
enum drx_carrier_mode {
|
|
DRX_CARRIER_MULTI = 0, /**< Multi carrier mode */
|
|
DRX_CARRIER_SINGLE, /**< Single carrier mode */
|
|
DRX_CARRIER_UNKNOWN = DRX_UNKNOWN,
|
|
/**< Carrier mode unknown. */
|
|
DRX_CARRIER_AUTO = DRX_AUTO /**< Autodetect carrier mode */
|
|
};
|
|
|
|
/**
|
|
* \enum enum drx_frame_mode
|
|
* \brief Channel Frame Mode.
|
|
*/
|
|
enum drx_frame_mode {
|
|
DRX_FRAMEMODE_420 = 0, /**< 420 with variable PN */
|
|
DRX_FRAMEMODE_595, /**< 595 */
|
|
DRX_FRAMEMODE_945, /**< 945 with variable PN */
|
|
DRX_FRAMEMODE_420_FIXED_PN,
|
|
/**< 420 with fixed PN */
|
|
DRX_FRAMEMODE_945_FIXED_PN,
|
|
/**< 945 with fixed PN */
|
|
DRX_FRAMEMODE_UNKNOWN = DRX_UNKNOWN,
|
|
/**< Frame mode unknown. */
|
|
DRX_FRAMEMODE_AUTO = DRX_AUTO
|
|
/**< Autodetect frame mode */
|
|
};
|
|
|
|
/**
|
|
* \enum enum drx_tps_frame
|
|
* \brief Frame number in current super-frame.
|
|
*/
|
|
enum drx_tps_frame {
|
|
DRX_TPS_FRAME1 = 0, /**< TPS frame 1. */
|
|
DRX_TPS_FRAME2, /**< TPS frame 2. */
|
|
DRX_TPS_FRAME3, /**< TPS frame 3. */
|
|
DRX_TPS_FRAME4, /**< TPS frame 4. */
|
|
DRX_TPS_FRAME_UNKNOWN = DRX_UNKNOWN
|
|
/**< TPS frame unknown. */
|
|
};
|
|
|
|
/**
|
|
* \enum enum drx_ldpc
|
|
* \brief TPS LDPC .
|
|
*/
|
|
enum drx_ldpc {
|
|
DRX_LDPC_0_4 = 0, /**< LDPC 0.4 */
|
|
DRX_LDPC_0_6, /**< LDPC 0.6 */
|
|
DRX_LDPC_0_8, /**< LDPC 0.8 */
|
|
DRX_LDPC_UNKNOWN = DRX_UNKNOWN,
|
|
/**< LDPC unknown. */
|
|
DRX_LDPC_AUTO = DRX_AUTO /**< Autodetect LDPC */
|
|
};
|
|
|
|
/**
|
|
* \enum enum drx_pilot_mode
|
|
* \brief Pilot modes in DTMB.
|
|
*/
|
|
enum drx_pilot_mode {
|
|
DRX_PILOT_ON = 0, /**< Pilot On */
|
|
DRX_PILOT_OFF, /**< Pilot Off */
|
|
DRX_PILOT_UNKNOWN = DRX_UNKNOWN,
|
|
/**< Pilot unknown. */
|
|
DRX_PILOT_AUTO = DRX_AUTO /**< Autodetect Pilot */
|
|
};
|
|
|
|
#define DRX_CTRL_BASE ((u32)0)
|
|
|
|
#define DRX_CTRL_NOP (DRX_CTRL_BASE + 0)/**< No Operation */
|
|
#define DRX_CTRL_PROBE_DEVICE (DRX_CTRL_BASE + 1)/**< Probe device */
|
|
|
|
#define DRX_CTRL_LOAD_UCODE (DRX_CTRL_BASE + 2)/**< Load microcode */
|
|
#define DRX_CTRL_VERIFY_UCODE (DRX_CTRL_BASE + 3)/**< Verify microcode */
|
|
#define DRX_CTRL_SET_CHANNEL (DRX_CTRL_BASE + 4)/**< Set channel */
|
|
#define DRX_CTRL_GET_CHANNEL (DRX_CTRL_BASE + 5)/**< Get channel */
|
|
#define DRX_CTRL_LOCK_STATUS (DRX_CTRL_BASE + 6)/**< Get lock status */
|
|
#define DRX_CTRL_SIG_QUALITY (DRX_CTRL_BASE + 7)/**< Get signal quality */
|
|
#define DRX_CTRL_SIG_STRENGTH (DRX_CTRL_BASE + 8)/**< Get signal strength*/
|
|
#define DRX_CTRL_RF_POWER (DRX_CTRL_BASE + 9)/**< Get RF power */
|
|
#define DRX_CTRL_CONSTEL (DRX_CTRL_BASE + 10)/**< Get constel point */
|
|
#define DRX_CTRL_SCAN_INIT (DRX_CTRL_BASE + 11)/**< Initialize scan */
|
|
#define DRX_CTRL_SCAN_NEXT (DRX_CTRL_BASE + 12)/**< Scan for next */
|
|
#define DRX_CTRL_SCAN_STOP (DRX_CTRL_BASE + 13)/**< Stop scan */
|
|
#define DRX_CTRL_TPS_INFO (DRX_CTRL_BASE + 14)/**< Get TPS info */
|
|
#define DRX_CTRL_SET_CFG (DRX_CTRL_BASE + 15)/**< Set configuration */
|
|
#define DRX_CTRL_GET_CFG (DRX_CTRL_BASE + 16)/**< Get configuration */
|
|
#define DRX_CTRL_VERSION (DRX_CTRL_BASE + 17)/**< Get version info */
|
|
#define DRX_CTRL_I2C_BRIDGE (DRX_CTRL_BASE + 18)/**< Open/close bridge */
|
|
#define DRX_CTRL_SET_STANDARD (DRX_CTRL_BASE + 19)/**< Set demod std */
|
|
#define DRX_CTRL_GET_STANDARD (DRX_CTRL_BASE + 20)/**< Get demod std */
|
|
#define DRX_CTRL_SET_OOB (DRX_CTRL_BASE + 21)/**< Set OOB param */
|
|
#define DRX_CTRL_GET_OOB (DRX_CTRL_BASE + 22)/**< Get OOB param */
|
|
#define DRX_CTRL_AUD_SET_STANDARD (DRX_CTRL_BASE + 23)/**< Set audio param */
|
|
#define DRX_CTRL_AUD_GET_STANDARD (DRX_CTRL_BASE + 24)/**< Get audio param */
|
|
#define DRX_CTRL_AUD_GET_STATUS (DRX_CTRL_BASE + 25)/**< Read RDS */
|
|
#define DRX_CTRL_AUD_BEEP (DRX_CTRL_BASE + 26)/**< Read RDS */
|
|
#define DRX_CTRL_I2C_READWRITE (DRX_CTRL_BASE + 27)/**< Read/write I2C */
|
|
#define DRX_CTRL_PROGRAM_TUNER (DRX_CTRL_BASE + 28)/**< Program tuner */
|
|
|
|
/* Professional */
|
|
#define DRX_CTRL_MB_CFG (DRX_CTRL_BASE + 29) /**< */
|
|
#define DRX_CTRL_MB_READ (DRX_CTRL_BASE + 30) /**< */
|
|
#define DRX_CTRL_MB_WRITE (DRX_CTRL_BASE + 31) /**< */
|
|
#define DRX_CTRL_MB_CONSTEL (DRX_CTRL_BASE + 32) /**< */
|
|
#define DRX_CTRL_MB_MER (DRX_CTRL_BASE + 33) /**< */
|
|
|
|
/* Misc */
|
|
#define DRX_CTRL_UIO_CFG DRX_CTRL_SET_UIO_CFG /**< Configure UIO */
|
|
#define DRX_CTRL_SET_UIO_CFG (DRX_CTRL_BASE + 34) /**< Configure UIO */
|
|
#define DRX_CTRL_GET_UIO_CFG (DRX_CTRL_BASE + 35) /**< Configure UIO */
|
|
#define DRX_CTRL_UIO_READ (DRX_CTRL_BASE + 36) /**< Read from UIO */
|
|
#define DRX_CTRL_UIO_WRITE (DRX_CTRL_BASE + 37) /**< Write to UIO */
|
|
#define DRX_CTRL_READ_EVENTS (DRX_CTRL_BASE + 38) /**< Read events */
|
|
#define DRX_CTRL_HDL_EVENTS (DRX_CTRL_BASE + 39) /**< Handle events */
|
|
#define DRX_CTRL_POWER_MODE (DRX_CTRL_BASE + 40) /**< Set power mode */
|
|
#define DRX_CTRL_LOAD_FILTER (DRX_CTRL_BASE + 41) /**< Load chan. filter */
|
|
#define DRX_CTRL_VALIDATE_UCODE (DRX_CTRL_BASE + 42) /**< Validate ucode */
|
|
#define DRX_CTRL_DUMP_REGISTERS (DRX_CTRL_BASE + 43) /**< Dump registers */
|
|
|
|
#define DRX_CTRL_MAX (DRX_CTRL_BASE + 44) /* never to be used */
|
|
|
|
/**
|
|
* \enum drxu_code_action_t
|
|
* \brief Used to indicate if firmware has to be uploaded or verified.
|
|
*/
|
|
|
|
typedef enum {
|
|
UCODE_UPLOAD,
|
|
/**< Upload the microcode image to device */
|
|
UCODE_VERIFY
|
|
/**< Compare microcode image with code on device */
|
|
} drxu_code_action_t, *pdrxu_code_action_t;
|
|
|
|
/**
|
|
* \enum drx_lock_status_t
|
|
* \brief Used to reflect current lock status of demodulator.
|
|
*
|
|
* The generic lock states have device dependent semantics.
|
|
*/
|
|
typedef enum {
|
|
DRX_NEVER_LOCK = 0,
|
|
/**< Device will never lock on this signal */
|
|
DRX_NOT_LOCKED,
|
|
/**< Device has no lock at all */
|
|
DRX_LOCK_STATE_1,
|
|
/**< Generic lock state */
|
|
DRX_LOCK_STATE_2,
|
|
/**< Generic lock state */
|
|
DRX_LOCK_STATE_3,
|
|
/**< Generic lock state */
|
|
DRX_LOCK_STATE_4,
|
|
/**< Generic lock state */
|
|
DRX_LOCK_STATE_5,
|
|
/**< Generic lock state */
|
|
DRX_LOCK_STATE_6,
|
|
/**< Generic lock state */
|
|
DRX_LOCK_STATE_7,
|
|
/**< Generic lock state */
|
|
DRX_LOCK_STATE_8,
|
|
/**< Generic lock state */
|
|
DRX_LOCK_STATE_9,
|
|
/**< Generic lock state */
|
|
DRX_LOCKED /**< Device is in lock */
|
|
} drx_lock_status_t, *pdrx_lock_status_t;
|
|
|
|
/**
|
|
* \enum DRXUIO_t
|
|
* \brief Used to address a User IO (UIO).
|
|
*/
|
|
typedef enum {
|
|
DRX_UIO1,
|
|
DRX_UIO2,
|
|
DRX_UIO3,
|
|
DRX_UIO4,
|
|
DRX_UIO5,
|
|
DRX_UIO6,
|
|
DRX_UIO7,
|
|
DRX_UIO8,
|
|
DRX_UIO9,
|
|
DRX_UIO10,
|
|
DRX_UIO11,
|
|
DRX_UIO12,
|
|
DRX_UIO13,
|
|
DRX_UIO14,
|
|
DRX_UIO15,
|
|
DRX_UIO16,
|
|
DRX_UIO17,
|
|
DRX_UIO18,
|
|
DRX_UIO19,
|
|
DRX_UIO20,
|
|
DRX_UIO21,
|
|
DRX_UIO22,
|
|
DRX_UIO23,
|
|
DRX_UIO24,
|
|
DRX_UIO25,
|
|
DRX_UIO26,
|
|
DRX_UIO27,
|
|
DRX_UIO28,
|
|
DRX_UIO29,
|
|
DRX_UIO30,
|
|
DRX_UIO31,
|
|
DRX_UIO32,
|
|
DRX_UIO_MAX = DRX_UIO32
|
|
} DRXUIO_t, *p_drxuio_t;
|
|
|
|
/**
|
|
* \enum drxuio_mode_t
|
|
* \brief Used to configure the modus oprandi of a UIO.
|
|
*
|
|
* DRX_UIO_MODE_FIRMWARE is an old uio mode.
|
|
* It is replaced by the modes DRX_UIO_MODE_FIRMWARE0 .. DRX_UIO_MODE_FIRMWARE9.
|
|
* To be backward compatible DRX_UIO_MODE_FIRMWARE is equivalent to
|
|
* DRX_UIO_MODE_FIRMWARE0.
|
|
*/
|
|
typedef enum {
|
|
DRX_UIO_MODE_DISABLE = 0x01,
|
|
/**< not used, pin is configured as input */
|
|
DRX_UIO_MODE_READWRITE = 0x02,
|
|
/**< used for read/write by application */
|
|
DRX_UIO_MODE_FIRMWARE = 0x04,
|
|
/**< controlled by firmware, function 0 */
|
|
DRX_UIO_MODE_FIRMWARE0 = DRX_UIO_MODE_FIRMWARE,
|
|
/**< same as above */
|
|
DRX_UIO_MODE_FIRMWARE1 = 0x08,
|
|
/**< controlled by firmware, function 1 */
|
|
DRX_UIO_MODE_FIRMWARE2 = 0x10,
|
|
/**< controlled by firmware, function 2 */
|
|
DRX_UIO_MODE_FIRMWARE3 = 0x20,
|
|
/**< controlled by firmware, function 3 */
|
|
DRX_UIO_MODE_FIRMWARE4 = 0x40,
|
|
/**< controlled by firmware, function 4 */
|
|
DRX_UIO_MODE_FIRMWARE5 = 0x80
|
|
/**< controlled by firmware, function 5 */
|
|
} drxuio_mode_t, *pdrxuio_mode_t;
|
|
|
|
/**
|
|
* \enum drxoob_downstream_standard_t
|
|
* \brief Used to select OOB standard.
|
|
*
|
|
* Based on ANSI 55-1 and 55-2
|
|
*/
|
|
typedef enum {
|
|
DRX_OOB_MODE_A = 0,
|
|
/**< ANSI 55-1 */
|
|
DRX_OOB_MODE_B_GRADE_A,
|
|
/**< ANSI 55-2 A */
|
|
DRX_OOB_MODE_B_GRADE_B
|
|
/**< ANSI 55-2 B */
|
|
} drxoob_downstream_standard_t, *pdrxoob_downstream_standard_t;
|
|
|
|
/*-------------------------------------------------------------------------
|
|
STRUCTS
|
|
-------------------------------------------------------------------------*/
|
|
|
|
/*============================================================================*/
|
|
/*============================================================================*/
|
|
/*== CTRL CFG related data structures ========================================*/
|
|
/*============================================================================*/
|
|
/*============================================================================*/
|
|
|
|
/**
|
|
* \enum drx_cfg_type_t
|
|
* \brief Generic configuration function identifiers.
|
|
*/
|
|
typedef u32 drx_cfg_type_t, *pdrx_cfg_type_t;
|
|
|
|
#ifndef DRX_CFG_BASE
|
|
#define DRX_CFG_BASE ((drx_cfg_type_t)0)
|
|
#endif
|
|
|
|
#define DRX_CFG_MPEG_OUTPUT (DRX_CFG_BASE + 0) /* MPEG TS output */
|
|
#define DRX_CFG_PKTERR (DRX_CFG_BASE + 1) /* Packet Error */
|
|
#define DRX_CFG_SYMCLK_OFFS (DRX_CFG_BASE + 2) /* Symbol Clk Offset */
|
|
#define DRX_CFG_SMA (DRX_CFG_BASE + 3) /* Smart Antenna */
|
|
#define DRX_CFG_PINSAFE (DRX_CFG_BASE + 4) /* Pin safe mode */
|
|
#define DRX_CFG_SUBSTANDARD (DRX_CFG_BASE + 5) /* substandard */
|
|
#define DRX_CFG_AUD_VOLUME (DRX_CFG_BASE + 6) /* volume */
|
|
#define DRX_CFG_AUD_RDS (DRX_CFG_BASE + 7) /* rds */
|
|
#define DRX_CFG_AUD_AUTOSOUND (DRX_CFG_BASE + 8) /* ASS & ASC */
|
|
#define DRX_CFG_AUD_ASS_THRES (DRX_CFG_BASE + 9) /* ASS Thresholds */
|
|
#define DRX_CFG_AUD_DEVIATION (DRX_CFG_BASE + 10) /* Deviation */
|
|
#define DRX_CFG_AUD_PRESCALE (DRX_CFG_BASE + 11) /* Prescale */
|
|
#define DRX_CFG_AUD_MIXER (DRX_CFG_BASE + 12) /* Mixer */
|
|
#define DRX_CFG_AUD_AVSYNC (DRX_CFG_BASE + 13) /* AVSync */
|
|
#define DRX_CFG_AUD_CARRIER (DRX_CFG_BASE + 14) /* Audio carriers */
|
|
#define DRX_CFG_I2S_OUTPUT (DRX_CFG_BASE + 15) /* I2S output */
|
|
#define DRX_CFG_ATV_STANDARD (DRX_CFG_BASE + 16) /* ATV standard */
|
|
#define DRX_CFG_SQI_SPEED (DRX_CFG_BASE + 17) /* SQI speed */
|
|
#define DRX_CTRL_CFG_MAX (DRX_CFG_BASE + 18) /* never to be used */
|
|
|
|
#define DRX_CFG_PINS_SAFE_MODE DRX_CFG_PINSAFE
|
|
/*============================================================================*/
|
|
/*============================================================================*/
|
|
/*== CTRL related data structures ============================================*/
|
|
/*============================================================================*/
|
|
/*============================================================================*/
|
|
|
|
/**
|
|
* \struct drxu_code_info_t
|
|
* \brief Parameters for microcode upload and verfiy.
|
|
*
|
|
* Used by DRX_CTRL_LOAD_UCODE and DRX_CTRL_VERIFY_UCODE
|
|
*/
|
|
typedef struct {
|
|
u8 *mc_data;
|
|
/**< Pointer to microcode image. */
|
|
u16 mc_size;
|
|
/**< Microcode image size. */
|
|
} drxu_code_info_t, *p_drxu_code_info_t;
|
|
|
|
/**
|
|
* \struct drx_mc_version_rec_t
|
|
* \brief Microcode version record
|
|
* Version numbers are stored in BCD format, as usual:
|
|
* o major number = bits 31-20 (first three nibbles of MSW)
|
|
* o minor number = bits 19-16 (fourth nibble of MSW)
|
|
* o patch number = bits 15-0 (remaining nibbles in LSW)
|
|
*
|
|
* The device type indicates for which the device is meant. It is based on the
|
|
* JTAG ID, using everything except the bond ID and the metal fix.
|
|
*
|
|
* Special values:
|
|
* - mc_dev_type == 0 => any device allowed
|
|
* - mc_base_version == 0.0.0 => full microcode (mc_version is the version)
|
|
* - mc_base_version != 0.0.0 => patch microcode, the base microcode version
|
|
* (mc_version is the version)
|
|
*/
|
|
#define AUX_VER_RECORD 0x8000
|
|
|
|
typedef struct {
|
|
u16 aux_type; /* type of aux data - 0x8000 for version record */
|
|
u32 mc_dev_type; /* device type, based on JTAG ID */
|
|
u32 mc_version; /* version of microcode */
|
|
u32 mc_base_version; /* in case of patch: the original microcode version */
|
|
} drx_mc_version_rec_t, *pdrx_mc_version_rec_t;
|
|
|
|
/*========================================*/
|
|
|
|
/**
|
|
* \struct drx_filter_info_t
|
|
* \brief Parameters for loading filter coefficients
|
|
*
|
|
* Used by DRX_CTRL_LOAD_FILTER
|
|
*/
|
|
typedef struct {
|
|
u8 *data_re;
|
|
/**< pointer to coefficients for RE */
|
|
u8 *data_im;
|
|
/**< pointer to coefficients for IM */
|
|
u16 size_re;
|
|
/**< size of coefficients for RE */
|
|
u16 size_im;
|
|
/**< size of coefficients for IM */
|
|
} drx_filter_info_t, *pdrx_filter_info_t;
|
|
|
|
/*========================================*/
|
|
|
|
/**
|
|
* \struct drx_channel_t
|
|
* \brief The set of parameters describing a single channel.
|
|
*
|
|
* Used by DRX_CTRL_SET_CHANNEL and DRX_CTRL_GET_CHANNEL.
|
|
* Only certain fields need to be used for a specfic standard.
|
|
*
|
|
*/
|
|
typedef struct {
|
|
s32 frequency;
|
|
/**< frequency in kHz */
|
|
enum drx_bandwidth bandwidth;
|
|
/**< bandwidth */
|
|
enum drx_mirror mirror; /**< mirrored or not on RF */
|
|
enum drx_modulation constellation;
|
|
/**< constellation */
|
|
enum drx_hierarchy hierarchy;
|
|
/**< hierarchy */
|
|
enum drx_priority priority; /**< priority */
|
|
enum drx_coderate coderate; /**< coderate */
|
|
enum drx_guard guard; /**< guard interval */
|
|
enum drx_fft_mode fftmode; /**< fftmode */
|
|
enum drx_classification classification;
|
|
/**< classification */
|
|
u32 symbolrate;
|
|
/**< symbolrate in symbols/sec */
|
|
enum drx_interleave_mode interleavemode;
|
|
/**< interleaveMode QAM */
|
|
enum drx_ldpc ldpc; /**< ldpc */
|
|
enum drx_carrier_mode carrier; /**< carrier */
|
|
enum drx_frame_mode framemode;
|
|
/**< frame mode */
|
|
enum drx_pilot_mode pilot; /**< pilot mode */
|
|
} drx_channel_t, *pdrx_channel_t;
|
|
|
|
/*========================================*/
|
|
|
|
/**
|
|
* \struct drx_sig_quality_t
|
|
* Signal quality metrics.
|
|
*
|
|
* Used by DRX_CTRL_SIG_QUALITY.
|
|
*/
|
|
typedef struct {
|
|
u16 MER; /**< in steps of 0.1 dB */
|
|
u32 pre_viterbi_ber;
|
|
/**< in steps of 1/scale_factor_ber */
|
|
u32 post_viterbi_ber;
|
|
/**< in steps of 1/scale_factor_ber */
|
|
u32 scale_factor_ber;
|
|
/**< scale factor for BER */
|
|
u16 packet_error;
|
|
/**< number of packet errors */
|
|
u32 post_reed_solomon_ber;
|
|
/**< in steps of 1/scale_factor_ber */
|
|
u32 pre_ldpc_ber;
|
|
/**< in steps of 1/scale_factor_ber */
|
|
u32 aver_iter;/**< in steps of 0.01 */
|
|
u16 indicator;
|
|
/**< indicative signal quality low=0..100=high */
|
|
} drx_sig_quality_t, *pdrx_sig_quality_t;
|
|
|
|
typedef enum {
|
|
DRX_SQI_SPEED_FAST = 0,
|
|
DRX_SQI_SPEED_MEDIUM,
|
|
DRX_SQI_SPEED_SLOW,
|
|
DRX_SQI_SPEED_UNKNOWN = DRX_UNKNOWN
|
|
} drx_cfg_sqi_speed_t, *pdrx_cfg_sqi_speed_t;
|
|
|
|
/*========================================*/
|
|
|
|
/**
|
|
* \struct drx_complex_t
|
|
* A complex number.
|
|
*
|
|
* Used by DRX_CTRL_CONSTEL.
|
|
*/
|
|
typedef struct {
|
|
s16 im;
|
|
/**< Imaginary part. */
|
|
s16 re;
|
|
/**< Real part. */
|
|
} drx_complex_t, *pdrx_complex_t;
|
|
|
|
/*========================================*/
|
|
|
|
/**
|
|
* \struct drx_frequency_plan_t
|
|
* Array element of a frequency plan.
|
|
*
|
|
* Used by DRX_CTRL_SCAN_INIT.
|
|
*/
|
|
typedef struct {
|
|
s32 first;
|
|
/**< First centre frequency in this band */
|
|
s32 last;
|
|
/**< Last centre frequency in this band */
|
|
s32 step;
|
|
/**< Stepping frequency in this band */
|
|
enum drx_bandwidth bandwidth;
|
|
/**< Bandwidth within this frequency band */
|
|
u16 ch_number;
|
|
/**< First channel number in this band, or first
|
|
index in ch_names */
|
|
char **ch_names;
|
|
/**< Optional list of channel names in this
|
|
band */
|
|
} drx_frequency_plan_t, *p_drx_frequency_plan_t;
|
|
|
|
/*========================================*/
|
|
|
|
/**
|
|
* \struct drx_frequency_plan_info_t
|
|
* Array element of a list of frequency plans.
|
|
*
|
|
* Used by frequency_plan.h
|
|
*/
|
|
typedef struct {
|
|
p_drx_frequency_plan_t freq_plan;
|
|
int freq_planSize;
|
|
char *freq_planName;
|
|
} drx_frequency_plan_info_t, *pdrx_frequency_plan_info_t;
|
|
|
|
/*========================================*/
|
|
|
|
/**
|
|
* /struct drx_scan_data_qam_t
|
|
* QAM specific scanning variables
|
|
*/
|
|
typedef struct {
|
|
u32 *symbolrate; /**< list of symbolrates to scan */
|
|
u16 symbolrate_size; /**< size of symbolrate array */
|
|
enum drx_modulation *constellation;
|
|
/**< list of constellations */
|
|
u16 constellation_size; /**< size of constellation array */
|
|
u16 if_agc_threshold; /**< thresholf for IF-AGC based
|
|
scanning filter */
|
|
} drx_scan_data_qam_t, *pdrx_scan_data_qam_t;
|
|
|
|
/*========================================*/
|
|
|
|
/**
|
|
* /struct drx_scan_data_atv_t
|
|
* ATV specific scanning variables
|
|
*/
|
|
typedef struct {
|
|
s16 svr_threshold;
|
|
/**< threshold of Sound/Video ratio in 0.1dB steps */
|
|
} drx_scan_data_atv_t, *pdrx_scan_data_atv_t;
|
|
|
|
/*========================================*/
|
|
|
|
/**
|
|
* \struct drx_scan_param_t
|
|
* Parameters for channel scan.
|
|
*
|
|
* Used by DRX_CTRL_SCAN_INIT.
|
|
*/
|
|
typedef struct {
|
|
p_drx_frequency_plan_t frequency_plan;
|
|
/**< Frequency plan (array)*/
|
|
u16 frequency_plan_size; /**< Number of bands */
|
|
u32 num_tries; /**< Max channels tried */
|
|
s32 skip; /**< Minimum frequency step to take
|
|
after a channel is found */
|
|
void *ext_params; /**< Standard specific params */
|
|
} drx_scan_param_t, *p_drx_scan_param_t;
|
|
|
|
/*========================================*/
|
|
|
|
/**
|
|
* \brief Scan commands.
|
|
* Used by scanning algorithms.
|
|
*/
|
|
typedef enum {
|
|
DRX_SCAN_COMMAND_INIT = 0,/**< Initialize scanning */
|
|
DRX_SCAN_COMMAND_NEXT, /**< Next scan */
|
|
DRX_SCAN_COMMAND_STOP /**< Stop scanning */
|
|
} drx_scan_command_t, *pdrx_scan_command_t;
|
|
|
|
/*========================================*/
|
|
|
|
/**
|
|
* \brief Inner scan function prototype.
|
|
*/
|
|
typedef int(*drx_scan_func_t) (void *scan_context,
|
|
drx_scan_command_t scan_command,
|
|
pdrx_channel_t scan_channel,
|
|
bool *get_next_channel);
|
|
|
|
/*========================================*/
|
|
|
|
/**
|
|
* \struct drxtps_info_t
|
|
* TPS information, DVB-T specific.
|
|
*
|
|
* Used by DRX_CTRL_TPS_INFO.
|
|
*/
|
|
typedef struct {
|
|
enum drx_fft_mode fftmode; /**< Fft mode */
|
|
enum drx_guard guard; /**< Guard interval */
|
|
enum drx_modulation constellation;
|
|
/**< Constellation */
|
|
enum drx_hierarchy hierarchy;
|
|
/**< Hierarchy */
|
|
enum drx_coderate high_coderate;
|
|
/**< High code rate */
|
|
enum drx_coderate low_coderate;
|
|
/**< Low cod rate */
|
|
enum drx_tps_frame frame; /**< Tps frame */
|
|
u8 length; /**< Length */
|
|
u16 cell_id; /**< Cell id */
|
|
} drxtps_info_t, *pdrxtps_info_t;
|
|
|
|
/*========================================*/
|
|
|
|
/**
|
|
* \brief Power mode of device.
|
|
*
|
|
* Used by DRX_CTRL_SET_POWER_MODE.
|
|
*/
|
|
typedef enum {
|
|
DRX_POWER_UP = 0,
|
|
/**< Generic , Power Up Mode */
|
|
DRX_POWER_MODE_1,
|
|
/**< Device specific , Power Up Mode */
|
|
DRX_POWER_MODE_2,
|
|
/**< Device specific , Power Up Mode */
|
|
DRX_POWER_MODE_3,
|
|
/**< Device specific , Power Up Mode */
|
|
DRX_POWER_MODE_4,
|
|
/**< Device specific , Power Up Mode */
|
|
DRX_POWER_MODE_5,
|
|
/**< Device specific , Power Up Mode */
|
|
DRX_POWER_MODE_6,
|
|
/**< Device specific , Power Up Mode */
|
|
DRX_POWER_MODE_7,
|
|
/**< Device specific , Power Up Mode */
|
|
DRX_POWER_MODE_8,
|
|
/**< Device specific , Power Up Mode */
|
|
|
|
DRX_POWER_MODE_9,
|
|
/**< Device specific , Power Down Mode */
|
|
DRX_POWER_MODE_10,
|
|
/**< Device specific , Power Down Mode */
|
|
DRX_POWER_MODE_11,
|
|
/**< Device specific , Power Down Mode */
|
|
DRX_POWER_MODE_12,
|
|
/**< Device specific , Power Down Mode */
|
|
DRX_POWER_MODE_13,
|
|
/**< Device specific , Power Down Mode */
|
|
DRX_POWER_MODE_14,
|
|
/**< Device specific , Power Down Mode */
|
|
DRX_POWER_MODE_15,
|
|
/**< Device specific , Power Down Mode */
|
|
DRX_POWER_MODE_16,
|
|
/**< Device specific , Power Down Mode */
|
|
DRX_POWER_DOWN = 255
|
|
/**< Generic , Power Down Mode */
|
|
} drx_power_mode_t, *pdrx_power_mode_t;
|
|
|
|
/*========================================*/
|
|
|
|
/**
|
|
* \enum drx_module_t
|
|
* \brief Software module identification.
|
|
*
|
|
* Used by DRX_CTRL_VERSION.
|
|
*/
|
|
typedef enum {
|
|
DRX_MODULE_DEVICE,
|
|
DRX_MODULE_MICROCODE,
|
|
DRX_MODULE_DRIVERCORE,
|
|
DRX_MODULE_DEVICEDRIVER,
|
|
DRX_MODULE_DAP,
|
|
DRX_MODULE_BSP_I2C,
|
|
DRX_MODULE_BSP_TUNER,
|
|
DRX_MODULE_BSP_HOST,
|
|
DRX_MODULE_UNKNOWN
|
|
} drx_module_t, *pdrx_module_t;
|
|
|
|
/**
|
|
* \enum drx_version_t
|
|
* \brief Version information of one software module.
|
|
*
|
|
* Used by DRX_CTRL_VERSION.
|
|
*/
|
|
typedef struct {
|
|
drx_module_t module_type;
|
|
/**< Type identifier of the module */
|
|
char *module_name;
|
|
/**< Name or description of module */
|
|
u16 v_major; /**< Major version number */
|
|
u16 v_minor; /**< Minor version number */
|
|
u16 v_patch; /**< Patch version number */
|
|
char *v_string; /**< Version as text string */
|
|
} drx_version_t, *pdrx_version_t;
|
|
|
|
/**
|
|
* \enum drx_version_list_t
|
|
* \brief List element of NULL terminated, linked list for version information.
|
|
*
|
|
* Used by DRX_CTRL_VERSION.
|
|
*/
|
|
typedef struct drx_version_list_s {
|
|
pdrx_version_t version;/**< Version information */
|
|
struct drx_version_list_s *next;
|
|
/**< Next list element */
|
|
} drx_version_list_t, *p_drx_version_list_t;
|
|
|
|
/*========================================*/
|
|
|
|
/**
|
|
* \brief Parameters needed to confiugure a UIO.
|
|
*
|
|
* Used by DRX_CTRL_UIO_CFG.
|
|
*/
|
|
typedef struct {
|
|
DRXUIO_t uio;
|
|
/**< UIO identifier */
|
|
drxuio_mode_t mode;
|
|
/**< UIO operational mode */
|
|
} drxuio_cfg_t, *pdrxuio_cfg_t;
|
|
|
|
/*========================================*/
|
|
|
|
/**
|
|
* \brief Parameters needed to read from or write to a UIO.
|
|
*
|
|
* Used by DRX_CTRL_UIO_READ and DRX_CTRL_UIO_WRITE.
|
|
*/
|
|
typedef struct {
|
|
DRXUIO_t uio;
|
|
/**< UIO identifier */
|
|
bool value;
|
|
/**< UIO value (true=1, false=0) */
|
|
} drxuio_data_t, *pdrxuio_data_t;
|
|
|
|
/*========================================*/
|
|
|
|
/**
|
|
* \brief Parameters needed to configure OOB.
|
|
*
|
|
* Used by DRX_CTRL_SET_OOB.
|
|
*/
|
|
typedef struct {
|
|
s32 frequency; /**< Frequency in kHz */
|
|
drxoob_downstream_standard_t standard;
|
|
/**< OOB standard */
|
|
bool spectrum_inverted; /**< If true, then spectrum
|
|
is inverted */
|
|
} DRXOOB_t, *p_drxoob_t;
|
|
|
|
/*========================================*/
|
|
|
|
/**
|
|
* \brief Metrics from OOB.
|
|
*
|
|
* Used by DRX_CTRL_GET_OOB.
|
|
*/
|
|
typedef struct {
|
|
s32 frequency; /**< Frequency in Khz */
|
|
drx_lock_status_t lock; /**< Lock status */
|
|
u32 mer; /**< MER */
|
|
s32 symbol_rate_offset; /**< Symbolrate offset in ppm */
|
|
} drxoob_status_t, *pdrxoob_status_t;
|
|
|
|
/*========================================*/
|
|
|
|
/**
|
|
* \brief Device dependent configuration data.
|
|
*
|
|
* Used by DRX_CTRL_SET_CFG and DRX_CTRL_GET_CFG.
|
|
* A sort of nested drx_ctrl() functionality for device specific controls.
|
|
*/
|
|
typedef struct {
|
|
drx_cfg_type_t cfg_type;
|
|
/**< Function identifier */
|
|
void *cfg_data;
|
|
/**< Function data */
|
|
} drx_cfg_t, *pdrx_cfg_t;
|
|
|
|
/*========================================*/
|
|
|
|
/**
|
|
* /struct DRXMpegStartWidth_t
|
|
* MStart width [nr MCLK cycles] for serial MPEG output.
|
|
*/
|
|
|
|
typedef enum {
|
|
DRX_MPEG_STR_WIDTH_1,
|
|
DRX_MPEG_STR_WIDTH_8
|
|
} drxmpeg_str_width_t, *pdrxmpeg_str_width_t;
|
|
|
|
/* CTRL CFG MPEG ouput */
|
|
/**
|
|
* \struct drx_cfg_mpeg_output_t
|
|
* \brief Configuartion parameters for MPEG output control.
|
|
*
|
|
* Used by DRX_CFG_MPEG_OUTPUT, in combination with DRX_CTRL_SET_CFG and
|
|
* DRX_CTRL_GET_CFG.
|
|
*/
|
|
|
|
typedef struct {
|
|
bool enable_mpeg_output;/**< If true, enable MPEG output */
|
|
bool insert_rs_byte; /**< If true, insert RS byte */
|
|
bool enable_parallel; /**< If true, parallel out otherwise
|
|
serial */
|
|
bool invert_data; /**< If true, invert DATA signals */
|
|
bool invert_err; /**< If true, invert ERR signal */
|
|
bool invert_str; /**< If true, invert STR signals */
|
|
bool invert_val; /**< If true, invert VAL signals */
|
|
bool invert_clk; /**< If true, invert CLK signals */
|
|
bool static_clk; /**< If true, static MPEG clockrate
|
|
will be used, otherwise clockrate
|
|
will adapt to the bitrate of the
|
|
TS */
|
|
u32 bitrate; /**< Maximum bitrate in b/s in case
|
|
static clockrate is selected */
|
|
drxmpeg_str_width_t width_str;
|
|
/**< MPEG start width */
|
|
} drx_cfg_mpeg_output_t, *pdrx_cfg_mpeg_output_t;
|
|
|
|
/* CTRL CFG SMA */
|
|
/**
|
|
* /struct drx_cfg_smaio_t
|
|
* smart antenna i/o.
|
|
*/
|
|
typedef enum drx_cfg_smaio_t {
|
|
DRX_SMA_OUTPUT = 0,
|
|
DRX_SMA_INPUT
|
|
} drx_cfg_smaio_t, *pdrx_cfg_smaio_t;
|
|
|
|
/**
|
|
* /struct drx_cfg_sma_t
|
|
* Set smart antenna.
|
|
*/
|
|
typedef struct {
|
|
drx_cfg_smaio_t io;
|
|
u16 ctrl_data;
|
|
bool smart_ant_inverted;
|
|
} drx_cfg_sma_t, *pdrx_cfg_sma_t;
|
|
|
|
/*========================================*/
|
|
|
|
/**
|
|
* \struct drxi2c_data_t
|
|
* \brief Data for I2C via 2nd or 3rd or etc I2C port.
|
|
*
|
|
* Used by DRX_CTRL_I2C_READWRITE.
|
|
* If port_nr is equal to primairy port_nr BSPI2C will be used.
|
|
*
|
|
*/
|
|
typedef struct {
|
|
u16 port_nr; /**< I2C port number */
|
|
struct i2c_device_addr *w_dev_addr;
|
|
/**< Write device address */
|
|
u16 w_count; /**< Size of write data in bytes */
|
|
u8 *wData; /**< Pointer to write data */
|
|
struct i2c_device_addr *r_dev_addr;
|
|
/**< Read device address */
|
|
u16 r_count; /**< Size of data to read in bytes */
|
|
u8 *r_data; /**< Pointer to read buffer */
|
|
} drxi2c_data_t, *pdrxi2c_data_t;
|
|
|
|
/*========================================*/
|
|
|
|
/**
|
|
* \enum drx_aud_standard_t
|
|
* \brief Audio standard identifier.
|
|
*
|
|
* Used by DRX_CTRL_SET_AUD.
|
|
*/
|
|
typedef enum {
|
|
DRX_AUD_STANDARD_BTSC, /**< set BTSC standard (USA) */
|
|
DRX_AUD_STANDARD_A2, /**< set A2-Korea FM Stereo */
|
|
DRX_AUD_STANDARD_EIAJ, /**< set to Japanese FM Stereo */
|
|
DRX_AUD_STANDARD_FM_STEREO,/**< set to FM-Stereo Radio */
|
|
DRX_AUD_STANDARD_M_MONO, /**< for 4.5 MHz mono detected */
|
|
DRX_AUD_STANDARD_D_K_MONO, /**< for 6.5 MHz mono detected */
|
|
DRX_AUD_STANDARD_BG_FM, /**< set BG_FM standard */
|
|
DRX_AUD_STANDARD_D_K1, /**< set D_K1 standard */
|
|
DRX_AUD_STANDARD_D_K2, /**< set D_K2 standard */
|
|
DRX_AUD_STANDARD_D_K3, /**< set D_K3 standard */
|
|
DRX_AUD_STANDARD_BG_NICAM_FM,
|
|
/**< set BG_NICAM_FM standard */
|
|
DRX_AUD_STANDARD_L_NICAM_AM,
|
|
/**< set L_NICAM_AM standard */
|
|
DRX_AUD_STANDARD_I_NICAM_FM,
|
|
/**< set I_NICAM_FM standard */
|
|
DRX_AUD_STANDARD_D_K_NICAM_FM,
|
|
/**< set D_K_NICAM_FM standard */
|
|
DRX_AUD_STANDARD_NOT_READY,/**< used to detect audio standard */
|
|
DRX_AUD_STANDARD_AUTO = DRX_AUTO,
|
|
/**< Automatic Standard Detection */
|
|
DRX_AUD_STANDARD_UNKNOWN = DRX_UNKNOWN
|
|
/**< used as auto and for readback */
|
|
} drx_aud_standard_t, *pdrx_aud_standard_t;
|
|
|
|
/* CTRL_AUD_GET_STATUS - drx_aud_status_t */
|
|
/**
|
|
* \enum drx_aud_nicam_status_t
|
|
* \brief Status of NICAM carrier.
|
|
*/
|
|
typedef enum {
|
|
DRX_AUD_NICAM_DETECTED = 0,
|
|
/**< NICAM carrier detected */
|
|
DRX_AUD_NICAM_NOT_DETECTED,
|
|
/**< NICAM carrier not detected */
|
|
DRX_AUD_NICAM_BAD /**< NICAM carrier bad quality */
|
|
} drx_aud_nicam_status_t, *pdrx_aud_nicam_status_t;
|
|
|
|
/**
|
|
* \struct drx_aud_status_t
|
|
* \brief Audio status characteristics.
|
|
*/
|
|
typedef struct {
|
|
bool stereo; /**< stereo detection */
|
|
bool carrier_a; /**< carrier A detected */
|
|
bool carrier_b; /**< carrier B detected */
|
|
bool sap; /**< sap / bilingual detection */
|
|
bool rds; /**< RDS data array present */
|
|
drx_aud_nicam_status_t nicam_status;
|
|
/**< status of NICAM carrier */
|
|
s8 fm_ident; /**< FM Identification value */
|
|
} drx_aud_status_t, *pdrx_aud_status_t;
|
|
|
|
/* CTRL_AUD_READ_RDS - DRXRDSdata_t */
|
|
|
|
/**
|
|
* \struct DRXRDSdata_t
|
|
* \brief Raw RDS data array.
|
|
*/
|
|
typedef struct {
|
|
bool valid; /**< RDS data validation */
|
|
u16 data[18]; /**< data from one RDS data array */
|
|
} drx_cfg_aud_rds_t, *pdrx_cfg_aud_rds_t;
|
|
|
|
/* DRX_CFG_AUD_VOLUME - drx_cfg_aud_volume_t - set/get */
|
|
/**
|
|
* \enum DRXAudAVCDecayTime_t
|
|
* \brief Automatic volume control configuration.
|
|
*/
|
|
typedef enum {
|
|
DRX_AUD_AVC_OFF, /**< Automatic volume control off */
|
|
DRX_AUD_AVC_DECAYTIME_8S, /**< level volume in 8 seconds */
|
|
DRX_AUD_AVC_DECAYTIME_4S, /**< level volume in 4 seconds */
|
|
DRX_AUD_AVC_DECAYTIME_2S, /**< level volume in 2 seconds */
|
|
DRX_AUD_AVC_DECAYTIME_20MS/**< level volume in 20 millisec */
|
|
} drx_aud_avc_mode_t, *pdrx_aud_avc_mode_t;
|
|
|
|
/**
|
|
* /enum DRXAudMaxAVCGain_t
|
|
* /brief Automatic volume control max gain in audio baseband.
|
|
*/
|
|
typedef enum {
|
|
DRX_AUD_AVC_MAX_GAIN_0DB, /**< maximum AVC gain 0 dB */
|
|
DRX_AUD_AVC_MAX_GAIN_6DB, /**< maximum AVC gain 6 dB */
|
|
DRX_AUD_AVC_MAX_GAIN_12DB /**< maximum AVC gain 12 dB */
|
|
} drx_aud_avc_max_gain_t, *pdrx_aud_avc_max_gain_t;
|
|
|
|
/**
|
|
* /enum DRXAudMaxAVCAtten_t
|
|
* /brief Automatic volume control max attenuation in audio baseband.
|
|
*/
|
|
typedef enum {
|
|
DRX_AUD_AVC_MAX_ATTEN_12DB,
|
|
/**< maximum AVC attenuation 12 dB */
|
|
DRX_AUD_AVC_MAX_ATTEN_18DB,
|
|
/**< maximum AVC attenuation 18 dB */
|
|
DRX_AUD_AVC_MAX_ATTEN_24DB/**< maximum AVC attenuation 24 dB */
|
|
} drx_aud_avc_max_atten_t, *pdrx_aud_avc_max_atten_t;
|
|
/**
|
|
* \struct drx_cfg_aud_volume_t
|
|
* \brief Audio volume configuration.
|
|
*/
|
|
typedef struct {
|
|
bool mute; /**< mute overrides volume setting */
|
|
s16 volume; /**< volume, range -114 to 12 dB */
|
|
drx_aud_avc_mode_t avc_mode; /**< AVC auto volume control mode */
|
|
u16 avc_ref_level; /**< AVC reference level */
|
|
drx_aud_avc_max_gain_t avc_max_gain;
|
|
/**< AVC max gain selection */
|
|
drx_aud_avc_max_atten_t avc_max_atten;
|
|
/**< AVC max attenuation selection */
|
|
s16 strength_left; /**< quasi-peak, left speaker */
|
|
s16 strength_right; /**< quasi-peak, right speaker */
|
|
} drx_cfg_aud_volume_t, *pdrx_cfg_aud_volume_t;
|
|
|
|
/* DRX_CFG_I2S_OUTPUT - drx_cfg_i2s_output_t - set/get */
|
|
/**
|
|
* \enum drxi2s_mode_t
|
|
* \brief I2S output mode.
|
|
*/
|
|
typedef enum {
|
|
DRX_I2S_MODE_MASTER, /**< I2S is in master mode */
|
|
DRX_I2S_MODE_SLAVE /**< I2S is in slave mode */
|
|
} drxi2s_mode_t, *pdrxi2s_mode_t;
|
|
|
|
/**
|
|
* \enum drxi2s_word_length_t
|
|
* \brief Width of I2S data.
|
|
*/
|
|
typedef enum {
|
|
DRX_I2S_WORDLENGTH_32 = 0,/**< I2S data is 32 bit wide */
|
|
DRX_I2S_WORDLENGTH_16 = 1 /**< I2S data is 16 bit wide */
|
|
} drxi2s_word_length_t, *pdrxi2s_word_length_t;
|
|
|
|
/**
|
|
* \enum drxi2s_format_t
|
|
* \brief Data wordstrobe alignment for I2S.
|
|
*/
|
|
typedef enum {
|
|
DRX_I2S_FORMAT_WS_WITH_DATA,
|
|
/**< I2S data and wordstrobe are aligned */
|
|
DRX_I2S_FORMAT_WS_ADVANCED
|
|
/**< I2S data one cycle after wordstrobe */
|
|
} drxi2s_format_t, *pdrxi2s_format_t;
|
|
|
|
/**
|
|
* \enum drxi2s_polarity_t
|
|
* \brief Polarity of I2S data.
|
|
*/
|
|
typedef enum {
|
|
DRX_I2S_POLARITY_RIGHT,/**< wordstrobe - right high, left low */
|
|
DRX_I2S_POLARITY_LEFT /**< wordstrobe - right low, left high */
|
|
} drxi2s_polarity_t, *pdrxi2s_polarity_t;
|
|
|
|
/**
|
|
* \struct drx_cfg_i2s_output_t
|
|
* \brief I2S output configuration.
|
|
*/
|
|
typedef struct {
|
|
bool output_enable; /**< I2S output enable */
|
|
u32 frequency; /**< range from 8000-48000 Hz */
|
|
drxi2s_mode_t mode; /**< I2S mode, master or slave */
|
|
drxi2s_word_length_t word_length;
|
|
/**< I2S wordlength, 16 or 32 bits */
|
|
drxi2s_polarity_t polarity;/**< I2S wordstrobe polarity */
|
|
drxi2s_format_t format; /**< I2S wordstrobe delay to data */
|
|
} drx_cfg_i2s_output_t, *pdrx_cfg_i2s_output_t;
|
|
|
|
/* ------------------------------expert interface-----------------------------*/
|
|
/**
|
|
* /enum drx_aud_fm_deemphasis_t
|
|
* setting for FM-Deemphasis in audio demodulator.
|
|
*
|
|
*/
|
|
typedef enum {
|
|
DRX_AUD_FM_DEEMPH_50US,
|
|
DRX_AUD_FM_DEEMPH_75US,
|
|
DRX_AUD_FM_DEEMPH_OFF
|
|
} drx_aud_fm_deemphasis_t, *pdrx_aud_fm_deemphasis_t;
|
|
|
|
/**
|
|
* /enum DRXAudDeviation_t
|
|
* setting for deviation mode in audio demodulator.
|
|
*
|
|
*/
|
|
typedef enum {
|
|
DRX_AUD_DEVIATION_NORMAL,
|
|
DRX_AUD_DEVIATION_HIGH
|
|
} drx_cfg_aud_deviation_t, *pdrx_cfg_aud_deviation_t;
|
|
|
|
/**
|
|
* /enum drx_no_carrier_option_t
|
|
* setting for carrier, mute/noise.
|
|
*
|
|
*/
|
|
typedef enum {
|
|
DRX_NO_CARRIER_MUTE,
|
|
DRX_NO_CARRIER_NOISE
|
|
} drx_no_carrier_option_t, *pdrx_no_carrier_option_t;
|
|
|
|
/**
|
|
* \enum DRXAudAutoSound_t
|
|
* \brief Automatic Sound
|
|
*/
|
|
typedef enum {
|
|
DRX_AUD_AUTO_SOUND_OFF = 0,
|
|
DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON,
|
|
DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF
|
|
} drx_cfg_aud_auto_sound_t, *pdrx_cfg_aud_auto_sound_t;
|
|
|
|
/**
|
|
* \enum DRXAudASSThres_t
|
|
* \brief Automatic Sound Select Thresholds
|
|
*/
|
|
typedef struct {
|
|
u16 a2; /* A2 Threshold for ASS configuration */
|
|
u16 btsc; /* BTSC Threshold for ASS configuration */
|
|
u16 nicam; /* Nicam Threshold for ASS configuration */
|
|
} drx_cfg_aud_ass_thres_t, *pdrx_cfg_aud_ass_thres_t;
|
|
|
|
/**
|
|
* \struct drx_aud_carrier_t
|
|
* \brief Carrier detection related parameters
|
|
*/
|
|
typedef struct {
|
|
u16 thres; /* carrier detetcion threshold for primary carrier (A) */
|
|
drx_no_carrier_option_t opt; /* Mute or noise at no carrier detection (A) */
|
|
s32 shift; /* DC level of incoming signal (A) */
|
|
s32 dco; /* frequency adjustment (A) */
|
|
} drx_aud_carrier_t, *p_drx_cfg_aud_carrier_t;
|
|
|
|
/**
|
|
* \struct drx_cfg_aud_carriers_t
|
|
* \brief combining carrier A & B to one struct
|
|
*/
|
|
typedef struct {
|
|
drx_aud_carrier_t a;
|
|
drx_aud_carrier_t b;
|
|
} drx_cfg_aud_carriers_t, *pdrx_cfg_aud_carriers_t;
|
|
|
|
/**
|
|
* /enum drx_aud_i2s_src_t
|
|
* Selection of audio source
|
|
*/
|
|
typedef enum {
|
|
DRX_AUD_SRC_MONO,
|
|
DRX_AUD_SRC_STEREO_OR_AB,
|
|
DRX_AUD_SRC_STEREO_OR_A,
|
|
DRX_AUD_SRC_STEREO_OR_B
|
|
} drx_aud_i2s_src_t, *pdrx_aud_i2s_src_t;
|
|
|
|
/**
|
|
* \enum drx_aud_i2s_matrix_t
|
|
* \brief Used for selecting I2S output.
|
|
*/
|
|
typedef enum {
|
|
DRX_AUD_I2S_MATRIX_A_MONO,
|
|
/**< A sound only, stereo or mono */
|
|
DRX_AUD_I2S_MATRIX_B_MONO,
|
|
/**< B sound only, stereo or mono */
|
|
DRX_AUD_I2S_MATRIX_STEREO,
|
|
/**< A+B sound, transparant */
|
|
DRX_AUD_I2S_MATRIX_MONO /**< A+B mixed to mono sum, (L+R)/2 */
|
|
} drx_aud_i2s_matrix_t, *pdrx_aud_i2s_matrix_t;
|
|
|
|
/**
|
|
* /enum drx_aud_fm_matrix_t
|
|
* setting for FM-Matrix in audio demodulator.
|
|
*
|
|
*/
|
|
typedef enum {
|
|
DRX_AUD_FM_MATRIX_NO_MATRIX,
|
|
DRX_AUD_FM_MATRIX_GERMAN,
|
|
DRX_AUD_FM_MATRIX_KOREAN,
|
|
DRX_AUD_FM_MATRIX_SOUND_A,
|
|
DRX_AUD_FM_MATRIX_SOUND_B
|
|
} drx_aud_fm_matrix_t, *pdrx_aud_fm_matrix_t;
|
|
|
|
/**
|
|
* \struct DRXAudMatrices_t
|
|
* \brief Mixer settings
|
|
*/
|
|
typedef struct {
|
|
drx_aud_i2s_src_t source_i2s;
|
|
drx_aud_i2s_matrix_t matrix_i2s;
|
|
drx_aud_fm_matrix_t matrix_fm;
|
|
} drx_cfg_aud_mixer_t, *pdrx_cfg_aud_mixer_t;
|
|
|
|
/**
|
|
* \enum DRXI2SVidSync_t
|
|
* \brief Audio/video synchronization, interacts with I2S mode.
|
|
* AUTO_1 and AUTO_2 are for automatic video standard detection with preference
|
|
* for NTSC or Monochrome, because the frequencies are too close (59.94 & 60 Hz)
|
|
*/
|
|
typedef enum {
|
|
DRX_AUD_AVSYNC_OFF,/**< audio/video synchronization is off */
|
|
DRX_AUD_AVSYNC_NTSC,
|
|
/**< it is an NTSC system */
|
|
DRX_AUD_AVSYNC_MONOCHROME,
|
|
/**< it is a MONOCHROME system */
|
|
DRX_AUD_AVSYNC_PAL_SECAM
|
|
/**< it is a PAL/SECAM system */
|
|
} drx_cfg_aud_av_sync_t, *pdrx_cfg_aud_av_sync_t;
|
|
|
|
/**
|
|
* \struct drx_cfg_aud_prescale_t
|
|
* \brief Prescalers
|
|
*/
|
|
typedef struct {
|
|
u16 fm_deviation;
|
|
s16 nicam_gain;
|
|
} drx_cfg_aud_prescale_t, *pdrx_cfg_aud_prescale_t;
|
|
|
|
/**
|
|
* \struct drx_aud_beep_t
|
|
* \brief Beep
|
|
*/
|
|
typedef struct {
|
|
s16 volume; /* dB */
|
|
u16 frequency; /* Hz */
|
|
bool mute;
|
|
} drx_aud_beep_t, *pdrx_aud_beep_t;
|
|
|
|
/**
|
|
* \enum drx_aud_btsc_detect_t
|
|
* \brief BTSC detetcion mode
|
|
*/
|
|
typedef enum {
|
|
DRX_BTSC_STEREO,
|
|
DRX_BTSC_MONO_AND_SAP
|
|
} drx_aud_btsc_detect_t, *pdrx_aud_btsc_detect_t;
|
|
|
|
/**
|
|
* \struct drx_aud_data_t
|
|
* \brief Audio data structure
|
|
*/
|
|
typedef struct {
|
|
/* audio storage */
|
|
bool audio_is_active;
|
|
drx_aud_standard_t audio_standard;
|
|
drx_cfg_i2s_output_t i2sdata;
|
|
drx_cfg_aud_volume_t volume;
|
|
drx_cfg_aud_auto_sound_t auto_sound;
|
|
drx_cfg_aud_ass_thres_t ass_thresholds;
|
|
drx_cfg_aud_carriers_t carriers;
|
|
drx_cfg_aud_mixer_t mixer;
|
|
drx_cfg_aud_deviation_t deviation;
|
|
drx_cfg_aud_av_sync_t av_sync;
|
|
drx_cfg_aud_prescale_t prescale;
|
|
drx_aud_fm_deemphasis_t deemph;
|
|
drx_aud_btsc_detect_t btsc_detect;
|
|
/* rds */
|
|
u16 rds_data_counter;
|
|
bool rds_data_present;
|
|
} drx_aud_data_t, *pdrx_aud_data_t;
|
|
|
|
/**
|
|
* \enum drx_qam_lock_range_t
|
|
* \brief QAM lock range mode
|
|
*/
|
|
typedef enum {
|
|
DRX_QAM_LOCKRANGE_NORMAL,
|
|
DRX_QAM_LOCKRANGE_EXTENDED
|
|
} drx_qam_lock_range_t, *pdrx_qam_lock_range_t;
|
|
|
|
/*============================================================================*/
|
|
/*============================================================================*/
|
|
/*== Data access structures ==================================================*/
|
|
/*============================================================================*/
|
|
/*============================================================================*/
|
|
|
|
/* Address on device */
|
|
typedef u32 dr_xaddr_t, *pdr_xaddr_t;
|
|
|
|
/* Protocol specific flags */
|
|
typedef u32 dr_xflags_t, *pdr_xflags_t;
|
|
|
|
/* Write block of data to device */
|
|
typedef int(*drx_write_block_func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
|
|
dr_xaddr_t addr, /* address of register/memory */
|
|
u16 datasize, /* size of data in bytes */
|
|
u8 *data, /* data to send */
|
|
dr_xflags_t flags);
|
|
|
|
/* Read block of data from device */
|
|
typedef int(*drx_read_block_func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
|
|
dr_xaddr_t addr, /* address of register/memory */
|
|
u16 datasize, /* size of data in bytes */
|
|
u8 *data, /* receive buffer */
|
|
dr_xflags_t flags);
|
|
|
|
/* Write 8-bits value to device */
|
|
typedef int(*drx_write_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
|
|
dr_xaddr_t addr, /* address of register/memory */
|
|
u8 data, /* data to send */
|
|
dr_xflags_t flags);
|
|
|
|
/* Read 8-bits value to device */
|
|
typedef int(*drx_read_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
|
|
dr_xaddr_t addr, /* address of register/memory */
|
|
u8 *data, /* receive buffer */
|
|
dr_xflags_t flags);
|
|
|
|
/* Read modify write 8-bits value to device */
|
|
typedef int(*drx_read_modify_write_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
|
|
dr_xaddr_t waddr, /* write address of register */
|
|
dr_xaddr_t raddr, /* read address of register */
|
|
u8 wdata, /* data to write */
|
|
u8 *rdata); /* data to read */
|
|
|
|
/* Write 16-bits value to device */
|
|
typedef int(*drx_write_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
|
|
dr_xaddr_t addr, /* address of register/memory */
|
|
u16 data, /* data to send */
|
|
dr_xflags_t flags);
|
|
|
|
/* Read 16-bits value to device */
|
|
typedef int(*drx_read_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
|
|
dr_xaddr_t addr, /* address of register/memory */
|
|
u16 *data, /* receive buffer */
|
|
dr_xflags_t flags);
|
|
|
|
/* Read modify write 16-bits value to device */
|
|
typedef int(*drx_read_modify_write_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
|
|
dr_xaddr_t waddr, /* write address of register */
|
|
dr_xaddr_t raddr, /* read address of register */
|
|
u16 wdata, /* data to write */
|
|
u16 *rdata); /* data to read */
|
|
|
|
/* Write 32-bits value to device */
|
|
typedef int(*drx_write_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
|
|
dr_xaddr_t addr, /* address of register/memory */
|
|
u32 data, /* data to send */
|
|
dr_xflags_t flags);
|
|
|
|
/* Read 32-bits value to device */
|
|
typedef int(*drx_read_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
|
|
dr_xaddr_t addr, /* address of register/memory */
|
|
u32 *data, /* receive buffer */
|
|
dr_xflags_t flags);
|
|
|
|
/* Read modify write 32-bits value to device */
|
|
typedef int(*drx_read_modify_write_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
|
|
dr_xaddr_t waddr, /* write address of register */
|
|
dr_xaddr_t raddr, /* read address of register */
|
|
u32 wdata, /* data to write */
|
|
u32 *rdata); /* data to read */
|
|
|
|
/**
|
|
* \struct drx_access_func_t
|
|
* \brief Interface to an access protocol.
|
|
*/
|
|
typedef struct {
|
|
pdrx_version_t protocolVersion;
|
|
drx_write_block_func_t write_block_func;
|
|
drx_read_block_func_t read_block_func;
|
|
drx_write_reg8func_t write_reg8func;
|
|
drx_read_reg8func_t read_reg8func;
|
|
drx_read_modify_write_reg8func_t read_modify_write_reg8func;
|
|
drx_write_reg16func_t write_reg16func;
|
|
drx_read_reg16func_t read_reg16func;
|
|
drx_read_modify_write_reg16func_t read_modify_write_reg16func;
|
|
drx_write_reg32func_t write_reg32func;
|
|
drx_read_reg32func_t read_reg32func;
|
|
drx_read_modify_write_reg32func_t read_modify_write_reg32func;
|
|
} drx_access_func_t, *pdrx_access_func_t;
|
|
|
|
/* Register address and data for register dump function */
|
|
typedef struct {
|
|
|
|
dr_xaddr_t address;
|
|
u32 data;
|
|
|
|
} drx_reg_dump_t, *p_drx_reg_dump_t;
|
|
|
|
/*============================================================================*/
|
|
/*============================================================================*/
|
|
/*== Demod instance data structures ==========================================*/
|
|
/*============================================================================*/
|
|
/*============================================================================*/
|
|
|
|
/**
|
|
* \struct drx_common_attr_t
|
|
* \brief Set of common attributes, shared by all DRX devices.
|
|
*/
|
|
typedef struct {
|
|
/* Microcode (firmware) attributes */
|
|
u8 *microcode; /**< Pointer to microcode image. */
|
|
u16 microcode_size;
|
|
/**< Size of microcode image in bytes. */
|
|
bool verify_microcode;
|
|
/**< Use microcode verify or not. */
|
|
drx_mc_version_rec_t mcversion;
|
|
/**< Version record of microcode from file */
|
|
|
|
/* Clocks and tuner attributes */
|
|
s32 intermediate_freq;
|
|
/**< IF,if tuner instance not used. (kHz)*/
|
|
s32 sys_clock_freq;
|
|
/**< Systemclock frequency. (kHz) */
|
|
s32 osc_clock_freq;
|
|
/**< Oscillator clock frequency. (kHz) */
|
|
s16 osc_clock_deviation;
|
|
/**< Oscillator clock deviation. (ppm) */
|
|
bool mirror_freq_spect;
|
|
/**< Mirror IF frequency spectrum or not.*/
|
|
|
|
/* Initial MPEG output attributes */
|
|
drx_cfg_mpeg_output_t mpeg_cfg;
|
|
/**< MPEG configuration */
|
|
|
|
bool is_opened; /**< if true instance is already opened. */
|
|
|
|
/* Channel scan */
|
|
p_drx_scan_param_t scan_param;
|
|
/**< scan parameters */
|
|
u16 scan_freq_plan_index;
|
|
/**< next index in freq plan */
|
|
s32 scan_next_frequency;
|
|
/**< next freq to scan */
|
|
bool scan_ready; /**< scan ready flag */
|
|
u32 scan_max_channels;/**< number of channels in freqplan */
|
|
u32 scan_channelsScanned;
|
|
/**< number of channels scanned */
|
|
/* Channel scan - inner loop: demod related */
|
|
drx_scan_func_t scan_function;
|
|
/**< function to check channel */
|
|
/* Channel scan - inner loop: SYSObj related */
|
|
void *scan_context; /**< Context Pointer of SYSObj */
|
|
/* Channel scan - parameters for default DTV scan function in core driver */
|
|
u16 scan_demod_lock_timeout;
|
|
/**< millisecs to wait for lock */
|
|
drx_lock_status_t scan_desired_lock;
|
|
/**< lock requirement for channel found */
|
|
/* scan_active can be used by SetChannel to decide how to program the tuner,
|
|
fast or slow (but stable). Usually fast during scan. */
|
|
bool scan_active; /**< true when scan routines are active */
|
|
|
|
/* Power management */
|
|
drx_power_mode_t current_power_mode;
|
|
/**< current power management mode */
|
|
|
|
/* Tuner */
|
|
u8 tuner_port_nr; /**< nr of I2C port to wich tuner is */
|
|
s32 tuner_min_freq_rf;
|
|
/**< minimum RF input frequency, in kHz */
|
|
s32 tuner_max_freq_rf;
|
|
/**< maximum RF input frequency, in kHz */
|
|
bool tuner_rf_agc_pol; /**< if true invert RF AGC polarity */
|
|
bool tuner_if_agc_pol; /**< if true invert IF AGC polarity */
|
|
bool tuner_slow_mode; /**< if true invert IF AGC polarity */
|
|
|
|
drx_channel_t current_channel;
|
|
/**< current channel parameters */
|
|
enum drx_standard current_standard;
|
|
/**< current standard selection */
|
|
enum drx_standard prev_standard;
|
|
/**< previous standard selection */
|
|
enum drx_standard di_cache_standard;
|
|
/**< standard in DI cache if available */
|
|
bool use_bootloader; /**< use bootloader in open */
|
|
u32 capabilities; /**< capabilities flags */
|
|
u32 product_id; /**< product ID inc. metal fix number */
|
|
|
|
} drx_common_attr_t, *pdrx_common_attr_t;
|
|
|
|
/*
|
|
* Generic functions for DRX devices.
|
|
*/
|
|
typedef struct drx_demod_instance_s *pdrx_demod_instance_t;
|
|
|
|
typedef int(*drx_open_func_t) (pdrx_demod_instance_t demod);
|
|
typedef int(*drx_close_func_t) (pdrx_demod_instance_t demod);
|
|
typedef int(*drx_ctrl_func_t) (pdrx_demod_instance_t demod,
|
|
u32 ctrl,
|
|
void *ctrl_data);
|
|
|
|
/**
|
|
* \struct drx_demod_func_t
|
|
* \brief A stucture containing all functions of a demodulator.
|
|
*/
|
|
typedef struct {
|
|
u32 type_id; /**< Device type identifier. */
|
|
drx_open_func_t open_func; /**< Pointer to Open() function. */
|
|
drx_close_func_t close_func;/**< Pointer to Close() function. */
|
|
drx_ctrl_func_t ctrl_func; /**< Pointer to Ctrl() function. */
|
|
} drx_demod_func_t, *pdrx_demod_func_t;
|
|
|
|
/**
|
|
* \struct drx_demod_instance_t
|
|
* \brief Top structure of demodulator instance.
|
|
*/
|
|
typedef struct drx_demod_instance_s {
|
|
/* type specific demodulator data */
|
|
pdrx_demod_func_t my_demod_funct;
|
|
/**< demodulator functions */
|
|
pdrx_access_func_t my_access_funct;
|
|
/**< data access protocol functions */
|
|
struct tuner_instance *my_tuner;
|
|
/**< tuner instance,if NULL then baseband */
|
|
struct i2c_device_addr *my_i2c_dev_addr;
|
|
/**< i2c address and device identifier */
|
|
pdrx_common_attr_t my_common_attr;
|
|
/**< common DRX attributes */
|
|
void *my_ext_attr; /**< device specific attributes */
|
|
/* generic demodulator data */
|
|
} drx_demod_instance_t;
|
|
|
|
/*-------------------------------------------------------------------------
|
|
MACROS
|
|
Conversion from enum values to human readable form.
|
|
-------------------------------------------------------------------------*/
|
|
|
|
/* standard */
|
|
|
|
#define DRX_STR_STANDARD(x) ( \
|
|
(x == DRX_STANDARD_DVBT) ? "DVB-T" : \
|
|
(x == DRX_STANDARD_8VSB) ? "8VSB" : \
|
|
(x == DRX_STANDARD_NTSC) ? "NTSC" : \
|
|
(x == DRX_STANDARD_PAL_SECAM_BG) ? "PAL/SECAM B/G" : \
|
|
(x == DRX_STANDARD_PAL_SECAM_DK) ? "PAL/SECAM D/K" : \
|
|
(x == DRX_STANDARD_PAL_SECAM_I) ? "PAL/SECAM I" : \
|
|
(x == DRX_STANDARD_PAL_SECAM_L) ? "PAL/SECAM L" : \
|
|
(x == DRX_STANDARD_PAL_SECAM_LP) ? "PAL/SECAM LP" : \
|
|
(x == DRX_STANDARD_ITU_A) ? "ITU-A" : \
|
|
(x == DRX_STANDARD_ITU_B) ? "ITU-B" : \
|
|
(x == DRX_STANDARD_ITU_C) ? "ITU-C" : \
|
|
(x == DRX_STANDARD_ITU_D) ? "ITU-D" : \
|
|
(x == DRX_STANDARD_FM) ? "FM" : \
|
|
(x == DRX_STANDARD_DTMB) ? "DTMB" : \
|
|
(x == DRX_STANDARD_AUTO) ? "Auto" : \
|
|
(x == DRX_STANDARD_UNKNOWN) ? "Unknown" : \
|
|
"(Invalid)")
|
|
|
|
/* channel */
|
|
|
|
#define DRX_STR_BANDWIDTH(x) ( \
|
|
(x == DRX_BANDWIDTH_8MHZ) ? "8 MHz" : \
|
|
(x == DRX_BANDWIDTH_7MHZ) ? "7 MHz" : \
|
|
(x == DRX_BANDWIDTH_6MHZ) ? "6 MHz" : \
|
|
(x == DRX_BANDWIDTH_AUTO) ? "Auto" : \
|
|
(x == DRX_BANDWIDTH_UNKNOWN) ? "Unknown" : \
|
|
"(Invalid)")
|
|
#define DRX_STR_FFTMODE(x) ( \
|
|
(x == DRX_FFTMODE_2K) ? "2k" : \
|
|
(x == DRX_FFTMODE_4K) ? "4k" : \
|
|
(x == DRX_FFTMODE_8K) ? "8k" : \
|
|
(x == DRX_FFTMODE_AUTO) ? "Auto" : \
|
|
(x == DRX_FFTMODE_UNKNOWN) ? "Unknown" : \
|
|
"(Invalid)")
|
|
#define DRX_STR_GUARD(x) ( \
|
|
(x == DRX_GUARD_1DIV32) ? "1/32nd" : \
|
|
(x == DRX_GUARD_1DIV16) ? "1/16th" : \
|
|
(x == DRX_GUARD_1DIV8) ? "1/8th" : \
|
|
(x == DRX_GUARD_1DIV4) ? "1/4th" : \
|
|
(x == DRX_GUARD_AUTO) ? "Auto" : \
|
|
(x == DRX_GUARD_UNKNOWN) ? "Unknown" : \
|
|
"(Invalid)")
|
|
#define DRX_STR_CONSTELLATION(x) ( \
|
|
(x == DRX_CONSTELLATION_BPSK) ? "BPSK" : \
|
|
(x == DRX_CONSTELLATION_QPSK) ? "QPSK" : \
|
|
(x == DRX_CONSTELLATION_PSK8) ? "PSK8" : \
|
|
(x == DRX_CONSTELLATION_QAM16) ? "QAM16" : \
|
|
(x == DRX_CONSTELLATION_QAM32) ? "QAM32" : \
|
|
(x == DRX_CONSTELLATION_QAM64) ? "QAM64" : \
|
|
(x == DRX_CONSTELLATION_QAM128) ? "QAM128" : \
|
|
(x == DRX_CONSTELLATION_QAM256) ? "QAM256" : \
|
|
(x == DRX_CONSTELLATION_QAM512) ? "QAM512" : \
|
|
(x == DRX_CONSTELLATION_QAM1024) ? "QAM1024" : \
|
|
(x == DRX_CONSTELLATION_QPSK_NR) ? "QPSK_NR" : \
|
|
(x == DRX_CONSTELLATION_AUTO) ? "Auto" : \
|
|
(x == DRX_CONSTELLATION_UNKNOWN) ? "Unknown" : \
|
|
"(Invalid)")
|
|
#define DRX_STR_CODERATE(x) ( \
|
|
(x == DRX_CODERATE_1DIV2) ? "1/2nd" : \
|
|
(x == DRX_CODERATE_2DIV3) ? "2/3rd" : \
|
|
(x == DRX_CODERATE_3DIV4) ? "3/4th" : \
|
|
(x == DRX_CODERATE_5DIV6) ? "5/6th" : \
|
|
(x == DRX_CODERATE_7DIV8) ? "7/8th" : \
|
|
(x == DRX_CODERATE_AUTO) ? "Auto" : \
|
|
(x == DRX_CODERATE_UNKNOWN) ? "Unknown" : \
|
|
"(Invalid)")
|
|
#define DRX_STR_HIERARCHY(x) ( \
|
|
(x == DRX_HIERARCHY_NONE) ? "None" : \
|
|
(x == DRX_HIERARCHY_ALPHA1) ? "Alpha=1" : \
|
|
(x == DRX_HIERARCHY_ALPHA2) ? "Alpha=2" : \
|
|
(x == DRX_HIERARCHY_ALPHA4) ? "Alpha=4" : \
|
|
(x == DRX_HIERARCHY_AUTO) ? "Auto" : \
|
|
(x == DRX_HIERARCHY_UNKNOWN) ? "Unknown" : \
|
|
"(Invalid)")
|
|
#define DRX_STR_PRIORITY(x) ( \
|
|
(x == DRX_PRIORITY_LOW) ? "Low" : \
|
|
(x == DRX_PRIORITY_HIGH) ? "High" : \
|
|
(x == DRX_PRIORITY_UNKNOWN) ? "Unknown" : \
|
|
"(Invalid)")
|
|
#define DRX_STR_MIRROR(x) ( \
|
|
(x == DRX_MIRROR_NO) ? "Normal" : \
|
|
(x == DRX_MIRROR_YES) ? "Mirrored" : \
|
|
(x == DRX_MIRROR_AUTO) ? "Auto" : \
|
|
(x == DRX_MIRROR_UNKNOWN) ? "Unknown" : \
|
|
"(Invalid)")
|
|
#define DRX_STR_CLASSIFICATION(x) ( \
|
|
(x == DRX_CLASSIFICATION_GAUSS) ? "Gaussion" : \
|
|
(x == DRX_CLASSIFICATION_HVY_GAUSS) ? "Heavy Gaussion" : \
|
|
(x == DRX_CLASSIFICATION_COCHANNEL) ? "Co-channel" : \
|
|
(x == DRX_CLASSIFICATION_STATIC) ? "Static echo" : \
|
|
(x == DRX_CLASSIFICATION_MOVING) ? "Moving echo" : \
|
|
(x == DRX_CLASSIFICATION_ZERODB) ? "Zero dB echo" : \
|
|
(x == DRX_CLASSIFICATION_UNKNOWN) ? "Unknown" : \
|
|
(x == DRX_CLASSIFICATION_AUTO) ? "Auto" : \
|
|
"(Invalid)")
|
|
|
|
#define DRX_STR_INTERLEAVEMODE(x) ( \
|
|
(x == DRX_INTERLEAVEMODE_I128_J1) ? "I128_J1" : \
|
|
(x == DRX_INTERLEAVEMODE_I128_J1_V2) ? "I128_J1_V2" : \
|
|
(x == DRX_INTERLEAVEMODE_I128_J2) ? "I128_J2" : \
|
|
(x == DRX_INTERLEAVEMODE_I64_J2) ? "I64_J2" : \
|
|
(x == DRX_INTERLEAVEMODE_I128_J3) ? "I128_J3" : \
|
|
(x == DRX_INTERLEAVEMODE_I32_J4) ? "I32_J4" : \
|
|
(x == DRX_INTERLEAVEMODE_I128_J4) ? "I128_J4" : \
|
|
(x == DRX_INTERLEAVEMODE_I16_J8) ? "I16_J8" : \
|
|
(x == DRX_INTERLEAVEMODE_I128_J5) ? "I128_J5" : \
|
|
(x == DRX_INTERLEAVEMODE_I8_J16) ? "I8_J16" : \
|
|
(x == DRX_INTERLEAVEMODE_I128_J6) ? "I128_J6" : \
|
|
(x == DRX_INTERLEAVEMODE_RESERVED_11) ? "Reserved 11" : \
|
|
(x == DRX_INTERLEAVEMODE_I128_J7) ? "I128_J7" : \
|
|
(x == DRX_INTERLEAVEMODE_RESERVED_13) ? "Reserved 13" : \
|
|
(x == DRX_INTERLEAVEMODE_I128_J8) ? "I128_J8" : \
|
|
(x == DRX_INTERLEAVEMODE_RESERVED_15) ? "Reserved 15" : \
|
|
(x == DRX_INTERLEAVEMODE_I12_J17) ? "I12_J17" : \
|
|
(x == DRX_INTERLEAVEMODE_I5_J4) ? "I5_J4" : \
|
|
(x == DRX_INTERLEAVEMODE_B52_M240) ? "B52_M240" : \
|
|
(x == DRX_INTERLEAVEMODE_B52_M720) ? "B52_M720" : \
|
|
(x == DRX_INTERLEAVEMODE_B52_M48) ? "B52_M48" : \
|
|
(x == DRX_INTERLEAVEMODE_B52_M0) ? "B52_M0" : \
|
|
(x == DRX_INTERLEAVEMODE_UNKNOWN) ? "Unknown" : \
|
|
(x == DRX_INTERLEAVEMODE_AUTO) ? "Auto" : \
|
|
"(Invalid)")
|
|
|
|
#define DRX_STR_LDPC(x) ( \
|
|
(x == DRX_LDPC_0_4) ? "0.4" : \
|
|
(x == DRX_LDPC_0_6) ? "0.6" : \
|
|
(x == DRX_LDPC_0_8) ? "0.8" : \
|
|
(x == DRX_LDPC_AUTO) ? "Auto" : \
|
|
(x == DRX_LDPC_UNKNOWN) ? "Unknown" : \
|
|
"(Invalid)")
|
|
|
|
#define DRX_STR_CARRIER(x) ( \
|
|
(x == DRX_CARRIER_MULTI) ? "Multi" : \
|
|
(x == DRX_CARRIER_SINGLE) ? "Single" : \
|
|
(x == DRX_CARRIER_AUTO) ? "Auto" : \
|
|
(x == DRX_CARRIER_UNKNOWN) ? "Unknown" : \
|
|
"(Invalid)")
|
|
|
|
#define DRX_STR_FRAMEMODE(x) ( \
|
|
(x == DRX_FRAMEMODE_420) ? "420" : \
|
|
(x == DRX_FRAMEMODE_595) ? "595" : \
|
|
(x == DRX_FRAMEMODE_945) ? "945" : \
|
|
(x == DRX_FRAMEMODE_420_FIXED_PN) ? "420 with fixed PN" : \
|
|
(x == DRX_FRAMEMODE_945_FIXED_PN) ? "945 with fixed PN" : \
|
|
(x == DRX_FRAMEMODE_AUTO) ? "Auto" : \
|
|
(x == DRX_FRAMEMODE_UNKNOWN) ? "Unknown" : \
|
|
"(Invalid)")
|
|
|
|
#define DRX_STR_PILOT(x) ( \
|
|
(x == DRX_PILOT_ON) ? "On" : \
|
|
(x == DRX_PILOT_OFF) ? "Off" : \
|
|
(x == DRX_PILOT_AUTO) ? "Auto" : \
|
|
(x == DRX_PILOT_UNKNOWN) ? "Unknown" : \
|
|
"(Invalid)")
|
|
/* TPS */
|
|
|
|
#define DRX_STR_TPS_FRAME(x) ( \
|
|
(x == DRX_TPS_FRAME1) ? "Frame1" : \
|
|
(x == DRX_TPS_FRAME2) ? "Frame2" : \
|
|
(x == DRX_TPS_FRAME3) ? "Frame3" : \
|
|
(x == DRX_TPS_FRAME4) ? "Frame4" : \
|
|
(x == DRX_TPS_FRAME_UNKNOWN) ? "Unknown" : \
|
|
"(Invalid)")
|
|
|
|
/* lock status */
|
|
|
|
#define DRX_STR_LOCKSTATUS(x) ( \
|
|
(x == DRX_NEVER_LOCK) ? "Never" : \
|
|
(x == DRX_NOT_LOCKED) ? "No" : \
|
|
(x == DRX_LOCKED) ? "Locked" : \
|
|
(x == DRX_LOCK_STATE_1) ? "Lock state 1" : \
|
|
(x == DRX_LOCK_STATE_2) ? "Lock state 2" : \
|
|
(x == DRX_LOCK_STATE_3) ? "Lock state 3" : \
|
|
(x == DRX_LOCK_STATE_4) ? "Lock state 4" : \
|
|
(x == DRX_LOCK_STATE_5) ? "Lock state 5" : \
|
|
(x == DRX_LOCK_STATE_6) ? "Lock state 6" : \
|
|
(x == DRX_LOCK_STATE_7) ? "Lock state 7" : \
|
|
(x == DRX_LOCK_STATE_8) ? "Lock state 8" : \
|
|
(x == DRX_LOCK_STATE_9) ? "Lock state 9" : \
|
|
"(Invalid)")
|
|
|
|
/* version information , modules */
|
|
#define DRX_STR_MODULE(x) ( \
|
|
(x == DRX_MODULE_DEVICE) ? "Device" : \
|
|
(x == DRX_MODULE_MICROCODE) ? "Microcode" : \
|
|
(x == DRX_MODULE_DRIVERCORE) ? "CoreDriver" : \
|
|
(x == DRX_MODULE_DEVICEDRIVER) ? "DeviceDriver" : \
|
|
(x == DRX_MODULE_BSP_I2C) ? "BSP I2C" : \
|
|
(x == DRX_MODULE_BSP_TUNER) ? "BSP Tuner" : \
|
|
(x == DRX_MODULE_BSP_HOST) ? "BSP Host" : \
|
|
(x == DRX_MODULE_DAP) ? "Data Access Protocol" : \
|
|
(x == DRX_MODULE_UNKNOWN) ? "Unknown" : \
|
|
"(Invalid)")
|
|
|
|
#define DRX_STR_POWER_MODE(x) ( \
|
|
(x == DRX_POWER_UP) ? "DRX_POWER_UP " : \
|
|
(x == DRX_POWER_MODE_1) ? "DRX_POWER_MODE_1" : \
|
|
(x == DRX_POWER_MODE_2) ? "DRX_POWER_MODE_2" : \
|
|
(x == DRX_POWER_MODE_3) ? "DRX_POWER_MODE_3" : \
|
|
(x == DRX_POWER_MODE_4) ? "DRX_POWER_MODE_4" : \
|
|
(x == DRX_POWER_MODE_5) ? "DRX_POWER_MODE_5" : \
|
|
(x == DRX_POWER_MODE_6) ? "DRX_POWER_MODE_6" : \
|
|
(x == DRX_POWER_MODE_7) ? "DRX_POWER_MODE_7" : \
|
|
(x == DRX_POWER_MODE_8) ? "DRX_POWER_MODE_8" : \
|
|
(x == DRX_POWER_MODE_9) ? "DRX_POWER_MODE_9" : \
|
|
(x == DRX_POWER_MODE_10) ? "DRX_POWER_MODE_10" : \
|
|
(x == DRX_POWER_MODE_11) ? "DRX_POWER_MODE_11" : \
|
|
(x == DRX_POWER_MODE_12) ? "DRX_POWER_MODE_12" : \
|
|
(x == DRX_POWER_MODE_13) ? "DRX_POWER_MODE_13" : \
|
|
(x == DRX_POWER_MODE_14) ? "DRX_POWER_MODE_14" : \
|
|
(x == DRX_POWER_MODE_15) ? "DRX_POWER_MODE_15" : \
|
|
(x == DRX_POWER_MODE_16) ? "DRX_POWER_MODE_16" : \
|
|
(x == DRX_POWER_DOWN) ? "DRX_POWER_DOWN " : \
|
|
"(Invalid)")
|
|
|
|
#define DRX_STR_OOB_STANDARD(x) ( \
|
|
(x == DRX_OOB_MODE_A) ? "ANSI 55-1 " : \
|
|
(x == DRX_OOB_MODE_B_GRADE_A) ? "ANSI 55-2 A" : \
|
|
(x == DRX_OOB_MODE_B_GRADE_B) ? "ANSI 55-2 B" : \
|
|
"(Invalid)")
|
|
|
|
#define DRX_STR_AUD_STANDARD(x) ( \
|
|
(x == DRX_AUD_STANDARD_BTSC) ? "BTSC" : \
|
|
(x == DRX_AUD_STANDARD_A2) ? "A2" : \
|
|
(x == DRX_AUD_STANDARD_EIAJ) ? "EIAJ" : \
|
|
(x == DRX_AUD_STANDARD_FM_STEREO) ? "FM Stereo" : \
|
|
(x == DRX_AUD_STANDARD_AUTO) ? "Auto" : \
|
|
(x == DRX_AUD_STANDARD_M_MONO) ? "M-Standard Mono" : \
|
|
(x == DRX_AUD_STANDARD_D_K_MONO) ? "D/K Mono FM" : \
|
|
(x == DRX_AUD_STANDARD_BG_FM) ? "B/G-Dual Carrier FM (A2)" : \
|
|
(x == DRX_AUD_STANDARD_D_K1) ? "D/K1-Dual Carrier FM" : \
|
|
(x == DRX_AUD_STANDARD_D_K2) ? "D/K2-Dual Carrier FM" : \
|
|
(x == DRX_AUD_STANDARD_D_K3) ? "D/K3-Dual Carrier FM" : \
|
|
(x == DRX_AUD_STANDARD_BG_NICAM_FM) ? "B/G-NICAM-FM" : \
|
|
(x == DRX_AUD_STANDARD_L_NICAM_AM) ? "L-NICAM-AM" : \
|
|
(x == DRX_AUD_STANDARD_I_NICAM_FM) ? "I-NICAM-FM" : \
|
|
(x == DRX_AUD_STANDARD_D_K_NICAM_FM) ? "D/K-NICAM-FM" : \
|
|
(x == DRX_AUD_STANDARD_UNKNOWN) ? "Unknown" : \
|
|
"(Invalid)")
|
|
#define DRX_STR_AUD_STEREO(x) ( \
|
|
(x == true) ? "Stereo" : \
|
|
(x == false) ? "Mono" : \
|
|
"(Invalid)")
|
|
|
|
#define DRX_STR_AUD_SAP(x) ( \
|
|
(x == true) ? "Present" : \
|
|
(x == false) ? "Not present" : \
|
|
"(Invalid)")
|
|
|
|
#define DRX_STR_AUD_CARRIER(x) ( \
|
|
(x == true) ? "Present" : \
|
|
(x == false) ? "Not present" : \
|
|
"(Invalid)")
|
|
|
|
#define DRX_STR_AUD_RDS(x) ( \
|
|
(x == true) ? "Available" : \
|
|
(x == false) ? "Not Available" : \
|
|
"(Invalid)")
|
|
|
|
#define DRX_STR_AUD_NICAM_STATUS(x) ( \
|
|
(x == DRX_AUD_NICAM_DETECTED) ? "Detected" : \
|
|
(x == DRX_AUD_NICAM_NOT_DETECTED) ? "Not detected" : \
|
|
(x == DRX_AUD_NICAM_BAD) ? "Bad" : \
|
|
"(Invalid)")
|
|
|
|
#define DRX_STR_RDS_VALID(x) ( \
|
|
(x == true) ? "Valid" : \
|
|
(x == false) ? "Not Valid" : \
|
|
"(Invalid)")
|
|
|
|
/*-------------------------------------------------------------------------
|
|
Access macros
|
|
-------------------------------------------------------------------------*/
|
|
|
|
/**
|
|
* \brief Create a compilable reference to the microcode attribute
|
|
* \param d pointer to demod instance
|
|
*
|
|
* Used as main reference to an attribute field.
|
|
* Used by both macro implementation and function implementation.
|
|
* These macros are defined to avoid duplication of code in macro and function
|
|
* definitions that handle access of demod common or extended attributes.
|
|
*
|
|
*/
|
|
|
|
#define DRX_ATTR_MCRECORD(d) ((d)->my_common_attr->mcversion)
|
|
#define DRX_ATTR_MIRRORFREQSPECT(d) ((d)->my_common_attr->mirror_freq_spect)
|
|
#define DRX_ATTR_CURRENTPOWERMODE(d)((d)->my_common_attr->current_power_mode)
|
|
#define DRX_ATTR_ISOPENED(d) ((d)->my_common_attr->is_opened)
|
|
#define DRX_ATTR_USEBOOTLOADER(d) ((d)->my_common_attr->use_bootloader)
|
|
#define DRX_ATTR_CURRENTSTANDARD(d) ((d)->my_common_attr->current_standard)
|
|
#define DRX_ATTR_PREVSTANDARD(d) ((d)->my_common_attr->prev_standard)
|
|
#define DRX_ATTR_CACHESTANDARD(d) ((d)->my_common_attr->di_cache_standard)
|
|
#define DRX_ATTR_CURRENTCHANNEL(d) ((d)->my_common_attr->current_channel)
|
|
#define DRX_ATTR_MICROCODE(d) ((d)->my_common_attr->microcode)
|
|
#define DRX_ATTR_MICROCODESIZE(d) ((d)->my_common_attr->microcode_size)
|
|
#define DRX_ATTR_VERIFYMICROCODE(d) ((d)->my_common_attr->verify_microcode)
|
|
#define DRX_ATTR_CAPABILITIES(d) ((d)->my_common_attr->capabilities)
|
|
#define DRX_ATTR_PRODUCTID(d) ((d)->my_common_attr->product_id)
|
|
#define DRX_ATTR_INTERMEDIATEFREQ(d) ((d)->my_common_attr->intermediate_freq)
|
|
#define DRX_ATTR_SYSCLOCKFREQ(d) ((d)->my_common_attr->sys_clock_freq)
|
|
#define DRX_ATTR_TUNERRFAGCPOL(d) ((d)->my_common_attr->tuner_rf_agc_pol)
|
|
#define DRX_ATTR_TUNERIFAGCPOL(d) ((d)->my_common_attr->tuner_if_agc_pol)
|
|
#define DRX_ATTR_TUNERSLOWMODE(d) ((d)->my_common_attr->tuner_slow_mode)
|
|
#define DRX_ATTR_TUNERSPORTNR(d) ((d)->my_common_attr->tuner_port_nr)
|
|
#define DRX_ATTR_TUNER(d) ((d)->my_tuner)
|
|
#define DRX_ATTR_I2CADDR(d) ((d)->my_i2c_dev_addr->i2c_addr)
|
|
#define DRX_ATTR_I2CDEVID(d) ((d)->my_i2c_dev_addr->i2c_dev_id)
|
|
|
|
/**
|
|
* \brief Actual access macro's
|
|
* \param d pointer to demod instance
|
|
* \param x value to set ar to get
|
|
*
|
|
* SET macro's must be used to set the value of an attribute.
|
|
* GET macro's must be used to retrieve the value of an attribute.
|
|
*
|
|
*/
|
|
|
|
/**************************/
|
|
|
|
#define DRX_SET_MIRRORFREQSPECT(d, x) \
|
|
do { \
|
|
DRX_ATTR_MIRRORFREQSPECT(d) = (x); \
|
|
} while (0)
|
|
|
|
#define DRX_GET_MIRRORFREQSPECT(d, x) \
|
|
do { \
|
|
(x) = DRX_ATTR_MIRRORFREQSPECT(d); \
|
|
} while (0)
|
|
|
|
/**************************/
|
|
|
|
#define DRX_SET_CURRENTPOWERMODE(d, x) \
|
|
do { \
|
|
DRX_ATTR_CURRENTPOWERMODE(d) = (x); \
|
|
} while (0)
|
|
|
|
#define DRX_GET_CURRENTPOWERMODE(d, x) \
|
|
do { \
|
|
(x) = DRX_ATTR_CURRENTPOWERMODE(d); \
|
|
} while (0)
|
|
|
|
/**************************/
|
|
|
|
#define DRX_SET_MICROCODE(d, x) \
|
|
do { \
|
|
DRX_ATTR_MICROCODE(d) = (x); \
|
|
} while (0)
|
|
|
|
#define DRX_GET_MICROCODE(d, x) \
|
|
do { \
|
|
(x) = DRX_ATTR_MICROCODE(d); \
|
|
} while (0)
|
|
|
|
/**************************/
|
|
|
|
#define DRX_SET_MICROCODESIZE(d, x) \
|
|
do { \
|
|
DRX_ATTR_MICROCODESIZE(d) = (x); \
|
|
} while (0)
|
|
|
|
#define DRX_GET_MICROCODESIZE(d, x) \
|
|
do { \
|
|
(x) = DRX_ATTR_MICROCODESIZE(d); \
|
|
} while (0)
|
|
|
|
/**************************/
|
|
|
|
#define DRX_SET_VERIFYMICROCODE(d, x) \
|
|
do { \
|
|
DRX_ATTR_VERIFYMICROCODE(d) = (x); \
|
|
} while (0)
|
|
|
|
#define DRX_GET_VERIFYMICROCODE(d, x) \
|
|
do { \
|
|
(x) = DRX_ATTR_VERIFYMICROCODE(d); \
|
|
} while (0)
|
|
|
|
/**************************/
|
|
|
|
#define DRX_SET_MCVERTYPE(d, x) \
|
|
do { \
|
|
DRX_ATTR_MCRECORD(d).aux_type = (x); \
|
|
} while (0)
|
|
|
|
#define DRX_GET_MCVERTYPE(d, x) \
|
|
do { \
|
|
(x) = DRX_ATTR_MCRECORD(d).aux_type; \
|
|
} while (0)
|
|
|
|
/**************************/
|
|
|
|
#define DRX_ISMCVERTYPE(x) ((x) == AUX_VER_RECORD)
|
|
|
|
/**************************/
|
|
|
|
#define DRX_SET_MCDEV(d, x) \
|
|
do { \
|
|
DRX_ATTR_MCRECORD(d).mc_dev_type = (x); \
|
|
} while (0)
|
|
|
|
#define DRX_GET_MCDEV(d, x) \
|
|
do { \
|
|
(x) = DRX_ATTR_MCRECORD(d).mc_dev_type; \
|
|
} while (0)
|
|
|
|
/**************************/
|
|
|
|
#define DRX_SET_MCVERSION(d, x) \
|
|
do { \
|
|
DRX_ATTR_MCRECORD(d).mc_version = (x); \
|
|
} while (0)
|
|
|
|
#define DRX_GET_MCVERSION(d, x) \
|
|
do { \
|
|
(x) = DRX_ATTR_MCRECORD(d).mc_version; \
|
|
} while (0)
|
|
|
|
/**************************/
|
|
#define DRX_SET_MCPATCH(d, x) \
|
|
do { \
|
|
DRX_ATTR_MCRECORD(d).mc_base_version = (x); \
|
|
} while (0)
|
|
|
|
#define DRX_GET_MCPATCH(d, x) \
|
|
do { \
|
|
(x) = DRX_ATTR_MCRECORD(d).mc_base_version; \
|
|
} while (0)
|
|
|
|
/**************************/
|
|
|
|
#define DRX_SET_I2CADDR(d, x) \
|
|
do { \
|
|
DRX_ATTR_I2CADDR(d) = (x); \
|
|
} while (0)
|
|
|
|
#define DRX_GET_I2CADDR(d, x) \
|
|
do { \
|
|
(x) = DRX_ATTR_I2CADDR(d); \
|
|
} while (0)
|
|
|
|
/**************************/
|
|
|
|
#define DRX_SET_I2CDEVID(d, x) \
|
|
do { \
|
|
DRX_ATTR_I2CDEVID(d) = (x); \
|
|
} while (0)
|
|
|
|
#define DRX_GET_I2CDEVID(d, x) \
|
|
do { \
|
|
(x) = DRX_ATTR_I2CDEVID(d); \
|
|
} while (0)
|
|
|
|
/**************************/
|
|
|
|
#define DRX_SET_USEBOOTLOADER(d, x) \
|
|
do { \
|
|
DRX_ATTR_USEBOOTLOADER(d) = (x); \
|
|
} while (0)
|
|
|
|
#define DRX_GET_USEBOOTLOADER(d, x) \
|
|
do { \
|
|
(x) = DRX_ATTR_USEBOOTLOADER(d); \
|
|
} while (0)
|
|
|
|
/**************************/
|
|
|
|
#define DRX_SET_CURRENTSTANDARD(d, x) \
|
|
do { \
|
|
DRX_ATTR_CURRENTSTANDARD(d) = (x); \
|
|
} while (0)
|
|
|
|
#define DRX_GET_CURRENTSTANDARD(d, x) \
|
|
do { \
|
|
(x) = DRX_ATTR_CURRENTSTANDARD(d); \
|
|
} while (0)
|
|
|
|
/**************************/
|
|
|
|
#define DRX_SET_PREVSTANDARD(d, x) \
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|
do { \
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|
DRX_ATTR_PREVSTANDARD(d) = (x); \
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|
} while (0)
|
|
|
|
#define DRX_GET_PREVSTANDARD(d, x) \
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|
do { \
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|
(x) = DRX_ATTR_PREVSTANDARD(d); \
|
|
} while (0)
|
|
|
|
/**************************/
|
|
|
|
#define DRX_SET_CACHESTANDARD(d, x) \
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|
do { \
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|
DRX_ATTR_CACHESTANDARD(d) = (x); \
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|
} while (0)
|
|
|
|
#define DRX_GET_CACHESTANDARD(d, x) \
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|
do { \
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|
(x) = DRX_ATTR_CACHESTANDARD(d); \
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|
} while (0)
|
|
|
|
/**************************/
|
|
|
|
#define DRX_SET_CURRENTCHANNEL(d, x) \
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|
do { \
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|
DRX_ATTR_CURRENTCHANNEL(d) = (x); \
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|
} while (0)
|
|
|
|
#define DRX_GET_CURRENTCHANNEL(d, x) \
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|
do { \
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|
(x) = DRX_ATTR_CURRENTCHANNEL(d); \
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|
} while (0)
|
|
|
|
/**************************/
|
|
|
|
#define DRX_SET_ISOPENED(d, x) \
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|
do { \
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|
DRX_ATTR_ISOPENED(d) = (x); \
|
|
} while (0)
|
|
|
|
#define DRX_GET_ISOPENED(d, x) \
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|
do { \
|
|
(x) = DRX_ATTR_ISOPENED(d); \
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|
} while (0)
|
|
|
|
/**************************/
|
|
|
|
#define DRX_SET_TUNER(d, x) \
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|
do { \
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|
DRX_ATTR_TUNER(d) = (x); \
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|
} while (0)
|
|
|
|
#define DRX_GET_TUNER(d, x) \
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|
do { \
|
|
(x) = DRX_ATTR_TUNER(d); \
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|
} while (0)
|
|
|
|
/**************************/
|
|
|
|
#define DRX_SET_CAPABILITIES(d, x) \
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|
do { \
|
|
DRX_ATTR_CAPABILITIES(d) = (x); \
|
|
} while (0)
|
|
|
|
#define DRX_GET_CAPABILITIES(d, x) \
|
|
do { \
|
|
(x) = DRX_ATTR_CAPABILITIES(d); \
|
|
} while (0)
|
|
|
|
/**************************/
|
|
|
|
#define DRX_SET_PRODUCTID(d, x) \
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|
do { \
|
|
DRX_ATTR_PRODUCTID(d) |= (x << 4); \
|
|
} while (0)
|
|
|
|
#define DRX_GET_PRODUCTID(d, x) \
|
|
do { \
|
|
(x) = (DRX_ATTR_PRODUCTID(d) >> 4); \
|
|
} while (0)
|
|
|
|
/**************************/
|
|
|
|
#define DRX_SET_MFX(d, x) \
|
|
do { \
|
|
DRX_ATTR_PRODUCTID(d) |= (x); \
|
|
} while (0)
|
|
|
|
#define DRX_GET_MFX(d, x) \
|
|
do { \
|
|
(x) = (DRX_ATTR_PRODUCTID(d) & 0xF); \
|
|
} while (0)
|
|
|
|
/**************************/
|
|
|
|
#define DRX_SET_INTERMEDIATEFREQ(d, x) \
|
|
do { \
|
|
DRX_ATTR_INTERMEDIATEFREQ(d) = (x); \
|
|
} while (0)
|
|
|
|
#define DRX_GET_INTERMEDIATEFREQ(d, x) \
|
|
do { \
|
|
(x) = DRX_ATTR_INTERMEDIATEFREQ(d); \
|
|
} while (0)
|
|
|
|
/**************************/
|
|
|
|
#define DRX_SET_SYSCLOCKFREQ(d, x) \
|
|
do { \
|
|
DRX_ATTR_SYSCLOCKFREQ(d) = (x); \
|
|
} while (0)
|
|
|
|
#define DRX_GET_SYSCLOCKFREQ(d, x) \
|
|
do { \
|
|
(x) = DRX_ATTR_SYSCLOCKFREQ(d); \
|
|
} while (0)
|
|
|
|
/**************************/
|
|
|
|
#define DRX_SET_TUNERRFAGCPOL(d, x) \
|
|
do { \
|
|
DRX_ATTR_TUNERRFAGCPOL(d) = (x); \
|
|
} while (0)
|
|
|
|
#define DRX_GET_TUNERRFAGCPOL(d, x) \
|
|
do { \
|
|
(x) = DRX_ATTR_TUNERRFAGCPOL(d); \
|
|
} while (0)
|
|
|
|
/**************************/
|
|
|
|
#define DRX_SET_TUNERIFAGCPOL(d, x) \
|
|
do { \
|
|
DRX_ATTR_TUNERIFAGCPOL(d) = (x); \
|
|
} while (0)
|
|
|
|
#define DRX_GET_TUNERIFAGCPOL(d, x) \
|
|
do { \
|
|
(x) = DRX_ATTR_TUNERIFAGCPOL(d); \
|
|
} while (0)
|
|
|
|
/**************************/
|
|
|
|
#define DRX_SET_TUNERSLOWMODE(d, x) \
|
|
do { \
|
|
DRX_ATTR_TUNERSLOWMODE(d) = (x); \
|
|
} while (0)
|
|
|
|
#define DRX_GET_TUNERSLOWMODE(d, x) \
|
|
do { \
|
|
(x) = DRX_ATTR_TUNERSLOWMODE(d); \
|
|
} while (0)
|
|
|
|
/**************************/
|
|
|
|
#define DRX_SET_TUNERPORTNR(d, x) \
|
|
do { \
|
|
DRX_ATTR_TUNERSPORTNR(d) = (x); \
|
|
} while (0)
|
|
|
|
/**************************/
|
|
|
|
/* Macros with device-specific handling are converted to CFG functions */
|
|
|
|
#define DRX_ACCESSMACRO_SET(demod, value, cfg_name, data_type) \
|
|
do { \
|
|
drx_cfg_t config; \
|
|
data_type cfg_data; \
|
|
config.cfg_type = cfg_name; \
|
|
config.cfg_data = &cfg_data; \
|
|
cfg_data = value; \
|
|
drx_ctrl(demod, DRX_CTRL_SET_CFG, &config); \
|
|
} while (0)
|
|
|
|
#define DRX_ACCESSMACRO_GET(demod, value, cfg_name, data_type, error_value) \
|
|
do { \
|
|
int cfg_status; \
|
|
drx_cfg_t config; \
|
|
data_type cfg_data; \
|
|
config.cfg_type = cfg_name; \
|
|
config.cfg_data = &cfg_data; \
|
|
cfg_status = drx_ctrl(demod, DRX_CTRL_GET_CFG, &config); \
|
|
if (cfg_status == DRX_STS_OK) { \
|
|
value = cfg_data; \
|
|
} else { \
|
|
value = (data_type)error_value; \
|
|
} \
|
|
} while (0)
|
|
|
|
/* Configuration functions for usage by Access (XS) Macros */
|
|
|
|
#ifndef DRX_XS_CFG_BASE
|
|
#define DRX_XS_CFG_BASE (500)
|
|
#endif
|
|
|
|
#define DRX_XS_CFG_PRESET (DRX_XS_CFG_BASE + 0)
|
|
#define DRX_XS_CFG_AUD_BTSC_DETECT (DRX_XS_CFG_BASE + 1)
|
|
#define DRX_XS_CFG_QAM_LOCKRANGE (DRX_XS_CFG_BASE + 2)
|
|
|
|
/* Access Macros with device-specific handling */
|
|
|
|
#define DRX_SET_PRESET(d, x) \
|
|
DRX_ACCESSMACRO_SET((d), (x), DRX_XS_CFG_PRESET, char*)
|
|
#define DRX_GET_PRESET(d, x) \
|
|
DRX_ACCESSMACRO_GET((d), (x), DRX_XS_CFG_PRESET, char*, "ERROR")
|
|
|
|
#define DRX_SET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_SET((d), (x), \
|
|
DRX_XS_CFG_AUD_BTSC_DETECT, drx_aud_btsc_detect_t)
|
|
#define DRX_GET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_GET((d), (x), \
|
|
DRX_XS_CFG_AUD_BTSC_DETECT, drx_aud_btsc_detect_t, DRX_UNKNOWN)
|
|
|
|
#define DRX_SET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_SET((d), (x), \
|
|
DRX_XS_CFG_QAM_LOCKRANGE, drx_qam_lock_range_t)
|
|
#define DRX_GET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_GET((d), (x), \
|
|
DRX_XS_CFG_QAM_LOCKRANGE, drx_qam_lock_range_t, DRX_UNKNOWN)
|
|
|
|
/**
|
|
* \brief Macro to check if std is an ATV standard
|
|
* \retval true std is an ATV standard
|
|
* \retval false std is an ATV standard
|
|
*/
|
|
#define DRX_ISATVSTD(std) (( (std) == DRX_STANDARD_PAL_SECAM_BG) || \
|
|
((std) == DRX_STANDARD_PAL_SECAM_DK) || \
|
|
((std) == DRX_STANDARD_PAL_SECAM_I) || \
|
|
((std) == DRX_STANDARD_PAL_SECAM_L) || \
|
|
((std) == DRX_STANDARD_PAL_SECAM_LP) || \
|
|
((std) == DRX_STANDARD_NTSC) || \
|
|
((std) == DRX_STANDARD_FM))
|
|
|
|
/**
|
|
* \brief Macro to check if std is an QAM standard
|
|
* \retval true std is an QAM standards
|
|
* \retval false std is an QAM standards
|
|
*/
|
|
#define DRX_ISQAMSTD(std) (( (std) == DRX_STANDARD_ITU_A) || \
|
|
((std) == DRX_STANDARD_ITU_B) || \
|
|
((std) == DRX_STANDARD_ITU_C) || \
|
|
((std) == DRX_STANDARD_ITU_D))
|
|
|
|
/**
|
|
* \brief Macro to check if std is VSB standard
|
|
* \retval true std is VSB standard
|
|
* \retval false std is not VSB standard
|
|
*/
|
|
#define DRX_ISVSBSTD(std) ((std) == DRX_STANDARD_8VSB)
|
|
|
|
/**
|
|
* \brief Macro to check if std is DVBT standard
|
|
* \retval true std is DVBT standard
|
|
* \retval false std is not DVBT standard
|
|
*/
|
|
#define DRX_ISDVBTSTD(std) ((std) == DRX_STANDARD_DVBT)
|
|
|
|
/*-------------------------------------------------------------------------
|
|
Exported FUNCTIONS
|
|
-------------------------------------------------------------------------*/
|
|
|
|
int drx_init(pdrx_demod_instance_t demods[]);
|
|
|
|
int drx_term(void);
|
|
|
|
int drx_open(pdrx_demod_instance_t demod);
|
|
|
|
int drx_close(pdrx_demod_instance_t demod);
|
|
|
|
int drx_ctrl(pdrx_demod_instance_t demod,
|
|
u32 ctrl, void *ctrl_data);
|
|
|
|
/*-------------------------------------------------------------------------
|
|
THE END
|
|
-------------------------------------------------------------------------*/
|
|
#endif /* __DRXDRIVER_H__ */
|