292 lines
7.4 KiB
C
292 lines
7.4 KiB
C
/*
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* Copyright (C) 2001,2002,2003 Broadcom Corporation
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* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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/*
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* BCM1250-specific PCI support
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*
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* This module provides the glue between Linux's PCI subsystem
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* and the hardware. We basically provide glue for accessing
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* configuration space, and set up the translation for I/O
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* space accesses.
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*
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* To access configuration space, we use ioremap. In the 32-bit
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* kernel, this consumes either 4 or 8 page table pages, and 16MB of
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* kernel mapped memory. Hopefully neither of these should be a huge
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* problem.
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/console.h>
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#include <linux/tty.h>
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#include <asm/io.h>
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#include <asm/sibyte/sb1250_defs.h>
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#include <asm/sibyte/sb1250_regs.h>
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#include <asm/sibyte/sb1250_scd.h>
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#include <asm/sibyte/board.h>
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/*
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* Macros for calculating offsets into config space given a device
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* structure or dev/fun/reg
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*/
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#define CFGOFFSET(bus, devfn, where) (((bus)<<16) + ((devfn)<<8) + (where))
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#define CFGADDR(bus, devfn, where) CFGOFFSET((bus)->number, (devfn), where)
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static void *cfg_space;
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#define PCI_BUS_ENABLED 1
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#define LDT_BUS_ENABLED 2
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#define PCI_DEVICE_MODE 4
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static int sb1250_bus_status = 0;
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#define PCI_BRIDGE_DEVICE 0
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#define LDT_BRIDGE_DEVICE 1
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#ifdef CONFIG_SIBYTE_HAS_LDT
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/*
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* HT's level-sensitive interrupts require EOI, which is generated
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* through a 4MB memory-mapped region
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*/
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unsigned long ldt_eoi_space;
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#endif
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/*
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* Read/write 32-bit values in config space.
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*/
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static inline u32 READCFG32(u32 addr)
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{
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return *(u32 *) (cfg_space + (addr & ~3));
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}
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static inline void WRITECFG32(u32 addr, u32 data)
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{
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*(u32 *) (cfg_space + (addr & ~3)) = data;
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}
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int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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return dev->irq;
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}
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/* Do platform specific device initialization at pci_enable_device() time */
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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return 0;
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}
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/*
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* Some checks before doing config cycles:
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* In PCI Device Mode, hide everything on bus 0 except the LDT host
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* bridge. Otherwise, access is controlled by bridge MasterEn bits.
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*/
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static int sb1250_pci_can_access(struct pci_bus *bus, int devfn)
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{
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u32 devno;
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if (!(sb1250_bus_status & (PCI_BUS_ENABLED | PCI_DEVICE_MODE)))
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return 0;
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if (bus->number == 0) {
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devno = PCI_SLOT(devfn);
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if (devno == LDT_BRIDGE_DEVICE)
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return (sb1250_bus_status & LDT_BUS_ENABLED) != 0;
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else if (sb1250_bus_status & PCI_DEVICE_MODE)
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return 0;
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else
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return 1;
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} else
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return 1;
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}
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/*
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* Read/write access functions for various sizes of values
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* in config space. Return all 1's for disallowed accesses
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* for a kludgy but adequate simulation of master aborts.
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*/
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static int sb1250_pcibios_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 * val)
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{
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u32 data = 0;
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if ((size == 2) && (where & 1))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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else if ((size == 4) && (where & 3))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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if (sb1250_pci_can_access(bus, devfn))
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data = READCFG32(CFGADDR(bus, devfn, where));
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else
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data = 0xFFFFFFFF;
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if (size == 1)
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*val = (data >> ((where & 3) << 3)) & 0xff;
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else if (size == 2)
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*val = (data >> ((where & 3) << 3)) & 0xffff;
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else
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*val = data;
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return PCIBIOS_SUCCESSFUL;
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}
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static int sb1250_pcibios_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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u32 cfgaddr = CFGADDR(bus, devfn, where);
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u32 data = 0;
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if ((size == 2) && (where & 1))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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else if ((size == 4) && (where & 3))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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if (!sb1250_pci_can_access(bus, devfn))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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data = READCFG32(cfgaddr);
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if (size == 1)
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data = (data & ~(0xff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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else if (size == 2)
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data = (data & ~(0xffff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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else
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data = val;
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WRITECFG32(cfgaddr, data);
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops sb1250_pci_ops = {
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.read = sb1250_pcibios_read,
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.write = sb1250_pcibios_write,
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};
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static struct resource sb1250_mem_resource = {
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.name = "SB1250 PCI MEM",
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.start = 0x40000000UL,
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.end = 0x5fffffffUL,
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.flags = IORESOURCE_MEM,
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};
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static struct resource sb1250_io_resource = {
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.name = "SB1250 PCI I/O",
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.start = 0x00000000UL,
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.end = 0x01ffffffUL,
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.flags = IORESOURCE_IO,
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};
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struct pci_controller sb1250_controller = {
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.pci_ops = &sb1250_pci_ops,
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.mem_resource = &sb1250_mem_resource,
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.io_resource = &sb1250_io_resource,
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};
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static int __init sb1250_pcibios_init(void)
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{
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uint32_t cmdreg;
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uint64_t reg;
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extern int pci_probe_only;
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/* CFE will assign PCI resources */
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pci_probe_only = 1;
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/* Avoid ISA compat ranges. */
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PCIBIOS_MIN_IO = 0x00008000UL;
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PCIBIOS_MIN_MEM = 0x01000000UL;
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/* Set I/O resource limits. */
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ioport_resource.end = 0x01ffffffUL; /* 32MB accessible by sb1250 */
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iomem_resource.end = 0xffffffffUL; /* no HT support yet */
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cfg_space =
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ioremap(A_PHYS_LDTPCI_CFG_MATCH_BITS, 16 * 1024 * 1024);
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/*
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* See if the PCI bus has been configured by the firmware.
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*/
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reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG));
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if (!(reg & M_SYS_PCI_HOST)) {
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sb1250_bus_status |= PCI_DEVICE_MODE;
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} else {
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cmdreg =
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READCFG32(CFGOFFSET
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(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0),
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PCI_COMMAND));
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if (!(cmdreg & PCI_COMMAND_MASTER)) {
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printk
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("PCI: Skipping PCI probe. Bus is not initialized.\n");
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iounmap(cfg_space);
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return 0;
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}
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sb1250_bus_status |= PCI_BUS_ENABLED;
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}
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/*
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* Establish mappings in KSEG2 (kernel virtual) to PCI I/O
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* space. Use "match bytes" policy to make everything look
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* little-endian. So, you need to also set
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* CONFIG_SWAP_IO_SPACE, but this is the combination that
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* works correctly with most of Linux's drivers.
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* XXX ehs: Should this happen in PCI Device mode?
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*/
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set_io_port_base((unsigned long)
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ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES, 65536));
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isa_slot_offset = (unsigned long)
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ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES_32, 1024 * 1024);
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#ifdef CONFIG_SIBYTE_HAS_LDT
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/*
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* Also check the LDT bridge's enable, just in case we didn't
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* initialize that one.
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*/
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cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(LDT_BRIDGE_DEVICE, 0),
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PCI_COMMAND));
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if (cmdreg & PCI_COMMAND_MASTER) {
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sb1250_bus_status |= LDT_BUS_ENABLED;
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/*
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* Need bits 23:16 to convey vector number. Note that
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* this consumes 4MB of kernel-mapped memory
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* (Kseg2/Kseg3) for 32-bit kernel.
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*/
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ldt_eoi_space = (unsigned long)
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ioremap(A_PHYS_LDT_SPECIAL_MATCH_BYTES,
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4 * 1024 * 1024);
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}
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#endif
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register_pci_controller(&sb1250_controller);
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#ifdef CONFIG_VGA_CONSOLE
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take_over_console(&vga_con, 0, MAX_NR_CONSOLES - 1, 1);
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#endif
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return 0;
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}
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arch_initcall(sb1250_pcibios_init);
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