285 lines
6.9 KiB
C
285 lines
6.9 KiB
C
#include <linux/dma-mapping.h>
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#include <linux/dma-debug.h>
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#include <linux/dmar.h>
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#include <linux/export.h>
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#include <linux/bootmem.h>
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#include <linux/gfp.h>
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#include <linux/pci.h>
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#include <linux/kmemleak.h>
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#include <asm/proto.h>
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#include <asm/dma.h>
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#include <asm/iommu.h>
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#include <asm/gart.h>
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#include <asm/calgary.h>
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#include <asm/x86_init.h>
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#include <asm/iommu_table.h>
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static int forbid_dac __read_mostly;
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struct dma_map_ops *dma_ops = &nommu_dma_ops;
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EXPORT_SYMBOL(dma_ops);
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static int iommu_sac_force __read_mostly;
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#ifdef CONFIG_IOMMU_DEBUG
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int panic_on_overflow __read_mostly = 1;
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int force_iommu __read_mostly = 1;
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#else
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int panic_on_overflow __read_mostly = 0;
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int force_iommu __read_mostly = 0;
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#endif
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int iommu_merge __read_mostly = 0;
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int no_iommu __read_mostly;
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/* Set this to 1 if there is a HW IOMMU in the system */
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int iommu_detected __read_mostly = 0;
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/*
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* This variable becomes 1 if iommu=pt is passed on the kernel command line.
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* If this variable is 1, IOMMU implementations do no DMA translation for
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* devices and allow every device to access to whole physical memory. This is
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* useful if a user wants to use an IOMMU only for KVM device assignment to
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* guests and not for driver dma translation.
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*/
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int iommu_pass_through __read_mostly;
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extern struct iommu_table_entry __iommu_table[], __iommu_table_end[];
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/* Dummy device used for NULL arguments (normally ISA). */
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struct device x86_dma_fallback_dev = {
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.init_name = "fallback device",
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.coherent_dma_mask = ISA_DMA_BIT_MASK,
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.dma_mask = &x86_dma_fallback_dev.coherent_dma_mask,
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};
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EXPORT_SYMBOL(x86_dma_fallback_dev);
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/* Number of entries preallocated for DMA-API debugging */
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#define PREALLOC_DMA_DEBUG_ENTRIES 65536
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int dma_set_mask(struct device *dev, u64 mask)
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{
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if (!dev->dma_mask || !dma_supported(dev, mask))
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return -EIO;
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*dev->dma_mask = mask;
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return 0;
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}
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EXPORT_SYMBOL(dma_set_mask);
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void __init pci_iommu_alloc(void)
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{
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struct iommu_table_entry *p;
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sort_iommu_table(__iommu_table, __iommu_table_end);
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check_iommu_entries(__iommu_table, __iommu_table_end);
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for (p = __iommu_table; p < __iommu_table_end; p++) {
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if (p && p->detect && p->detect() > 0) {
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p->flags |= IOMMU_DETECTED;
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if (p->early_init)
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p->early_init();
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if (p->flags & IOMMU_FINISH_IF_DETECTED)
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break;
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}
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}
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}
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void *dma_generic_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_addr, gfp_t flag,
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struct dma_attrs *attrs)
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{
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unsigned long dma_mask;
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struct page *page;
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unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
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dma_addr_t addr;
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dma_mask = dma_alloc_coherent_mask(dev, flag);
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flag &= ~__GFP_ZERO;
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again:
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page = NULL;
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/* CMA can be used only in the context which permits sleeping */
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if (flag & __GFP_WAIT) {
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page = dma_alloc_from_contiguous(dev, count, get_order(size));
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if (page && page_to_phys(page) + size > dma_mask) {
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dma_release_from_contiguous(dev, page, count);
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page = NULL;
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}
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}
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/* fallback */
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if (!page)
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page = alloc_pages_node(dev_to_node(dev), flag, get_order(size));
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if (!page)
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return NULL;
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addr = page_to_phys(page);
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if (addr + size > dma_mask) {
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__free_pages(page, get_order(size));
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if (dma_mask < DMA_BIT_MASK(32) && !(flag & GFP_DMA)) {
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flag = (flag & ~GFP_DMA32) | GFP_DMA;
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goto again;
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}
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return NULL;
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}
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memset(page_address(page), 0, size);
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*dma_addr = addr;
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return page_address(page);
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}
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void dma_generic_free_coherent(struct device *dev, size_t size, void *vaddr,
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dma_addr_t dma_addr, struct dma_attrs *attrs)
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{
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unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
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struct page *page = virt_to_page(vaddr);
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if (!dma_release_from_contiguous(dev, page, count))
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free_pages((unsigned long)vaddr, get_order(size));
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}
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/*
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* See <Documentation/x86/x86_64/boot-options.txt> for the iommu kernel
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* parameter documentation.
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*/
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static __init int iommu_setup(char *p)
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{
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iommu_merge = 1;
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if (!p)
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return -EINVAL;
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while (*p) {
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if (!strncmp(p, "off", 3))
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no_iommu = 1;
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/* gart_parse_options has more force support */
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if (!strncmp(p, "force", 5))
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force_iommu = 1;
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if (!strncmp(p, "noforce", 7)) {
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iommu_merge = 0;
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force_iommu = 0;
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}
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if (!strncmp(p, "biomerge", 8)) {
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iommu_merge = 1;
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force_iommu = 1;
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}
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if (!strncmp(p, "panic", 5))
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panic_on_overflow = 1;
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if (!strncmp(p, "nopanic", 7))
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panic_on_overflow = 0;
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if (!strncmp(p, "merge", 5)) {
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iommu_merge = 1;
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force_iommu = 1;
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}
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if (!strncmp(p, "nomerge", 7))
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iommu_merge = 0;
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if (!strncmp(p, "forcesac", 8))
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iommu_sac_force = 1;
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if (!strncmp(p, "allowdac", 8))
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forbid_dac = 0;
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if (!strncmp(p, "nodac", 5))
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forbid_dac = 1;
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if (!strncmp(p, "usedac", 6)) {
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forbid_dac = -1;
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return 1;
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}
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#ifdef CONFIG_SWIOTLB
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if (!strncmp(p, "soft", 4))
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swiotlb = 1;
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#endif
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if (!strncmp(p, "pt", 2))
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iommu_pass_through = 1;
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gart_parse_options(p);
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#ifdef CONFIG_CALGARY_IOMMU
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if (!strncmp(p, "calgary", 7))
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use_calgary = 1;
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#endif /* CONFIG_CALGARY_IOMMU */
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p += strcspn(p, ",");
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if (*p == ',')
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++p;
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}
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return 0;
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}
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early_param("iommu", iommu_setup);
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int dma_supported(struct device *dev, u64 mask)
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{
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struct dma_map_ops *ops = get_dma_ops(dev);
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#ifdef CONFIG_PCI
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if (mask > 0xffffffff && forbid_dac > 0) {
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dev_info(dev, "PCI: Disallowing DAC for device\n");
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return 0;
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}
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#endif
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if (ops->dma_supported)
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return ops->dma_supported(dev, mask);
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/* Copied from i386. Doesn't make much sense, because it will
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only work for pci_alloc_coherent.
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The caller just has to use GFP_DMA in this case. */
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if (mask < DMA_BIT_MASK(24))
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return 0;
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/* Tell the device to use SAC when IOMMU force is on. This
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allows the driver to use cheaper accesses in some cases.
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Problem with this is that if we overflow the IOMMU area and
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return DAC as fallback address the device may not handle it
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correctly.
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As a special case some controllers have a 39bit address
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mode that is as efficient as 32bit (aic79xx). Don't force
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SAC for these. Assume all masks <= 40 bits are of this
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type. Normally this doesn't make any difference, but gives
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more gentle handling of IOMMU overflow. */
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if (iommu_sac_force && (mask >= DMA_BIT_MASK(40))) {
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dev_info(dev, "Force SAC with mask %Lx\n", mask);
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return 0;
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}
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return 1;
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}
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EXPORT_SYMBOL(dma_supported);
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static int __init pci_iommu_init(void)
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{
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struct iommu_table_entry *p;
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dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
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#ifdef CONFIG_PCI
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dma_debug_add_bus(&pci_bus_type);
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#endif
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x86_init.iommu.iommu_init();
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for (p = __iommu_table; p < __iommu_table_end; p++) {
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if (p && (p->flags & IOMMU_DETECTED) && p->late_init)
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p->late_init();
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}
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return 0;
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}
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/* Must execute after PCI subsystem */
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rootfs_initcall(pci_iommu_init);
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#ifdef CONFIG_PCI
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/* Many VIA bridges seem to corrupt data for DAC. Disable it here */
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static void via_no_dac(struct pci_dev *dev)
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{
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if (forbid_dac == 0) {
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dev_info(&dev->dev, "disabling DAC on VIA PCI bridge\n");
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forbid_dac = 1;
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}
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}
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DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
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PCI_CLASS_BRIDGE_PCI, 8, via_no_dac);
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#endif
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