298 lines
7.3 KiB
C
298 lines
7.3 KiB
C
/*
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* arch/arm/mach-ixp2000/ixdp2800.c
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*
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* IXDP2800 platform support
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*
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* Original Author: Jeffrey Daly <jeffrey.daly@intel.com>
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* Maintainer: Deepak Saxena <dsaxena@plexity.net>
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*
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* Copyright (C) 2002 Intel Corp.
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* Copyright (C) 2003-2004 MontaVista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/device.h>
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#include <linux/bitops.h>
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#include <linux/pci.h>
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#include <linux/ioport.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/system.h>
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#include <asm/hardware.h>
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#include <asm/mach-types.h>
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#include <asm/mach/pci.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/time.h>
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#include <asm/mach/flash.h>
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#include <asm/mach/arch.h>
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/*************************************************************************
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* IXDP2800 timer tick
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*************************************************************************/
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static void __init ixdp2800_timer_init(void)
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{
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ixp2000_init_time(50000000);
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}
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static struct sys_timer ixdp2800_timer = {
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.init = ixdp2800_timer_init,
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.offset = ixp2000_gettimeoffset,
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};
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/*************************************************************************
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* IXDP2800 PCI
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*************************************************************************/
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static void __init ixdp2800_slave_disable_pci_master(void)
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{
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*IXP2000_PCI_CMDSTAT &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
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}
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static void __init ixdp2800_master_wait_for_slave(void)
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{
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volatile u32 *addr;
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printk(KERN_INFO "IXDP2800: waiting for slave NPU to configure "
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"its BAR sizes\n");
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addr = ixp2000_pci_config_addr(0, IXDP2X00_SLAVE_NPU_DEVFN,
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PCI_BASE_ADDRESS_1);
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do {
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*addr = 0xffffffff;
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cpu_relax();
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} while (*addr != 0xfe000008);
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addr = ixp2000_pci_config_addr(0, IXDP2X00_SLAVE_NPU_DEVFN,
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PCI_BASE_ADDRESS_2);
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do {
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*addr = 0xffffffff;
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cpu_relax();
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} while (*addr != 0xc0000008);
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/*
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* Configure the slave's SDRAM BAR by hand.
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*/
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*addr = 0x40000008;
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}
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static void __init ixdp2800_slave_wait_for_master_enable(void)
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{
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printk(KERN_INFO "IXDP2800: waiting for master NPU to enable us\n");
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while ((*IXP2000_PCI_CMDSTAT & PCI_COMMAND_MASTER) == 0)
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cpu_relax();
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}
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void __init ixdp2800_pci_preinit(void)
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{
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printk("ixdp2x00_pci_preinit called\n");
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*IXP2000_PCI_ADDR_EXT = 0x0001e000;
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if (!ixdp2x00_master_npu())
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ixdp2800_slave_disable_pci_master();
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*IXP2000_PCI_SRAM_BASE_ADDR_MASK = (0x2000000 - 1) & ~0x3ffff;
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*IXP2000_PCI_DRAM_BASE_ADDR_MASK = (0x40000000 - 1) & ~0xfffff;
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ixp2000_pci_preinit();
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if (ixdp2x00_master_npu()) {
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/*
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* Wait until the slave set its SRAM/SDRAM BAR sizes
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* correctly before we proceed to scan and enumerate
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* the bus.
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*/
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ixdp2800_master_wait_for_slave();
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/*
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* We configure the SDRAM BARs by hand because they
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* are 1G and fall outside of the regular allocated
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* PCI address space.
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*/
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*IXP2000_PCI_SDRAM_BAR = 0x00000008;
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} else {
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/*
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* Wait for the master to complete scanning the bus
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* and assigning resources before we proceed to scan
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* the bus ourselves. Set pci=firmware to honor the
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* master's resource assignment.
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*/
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ixdp2800_slave_wait_for_master_enable();
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pcibios_setup("firmware");
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}
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}
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/*
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* We assign the SDRAM BARs for the two IXP2800 CPUs by hand, outside
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* of the regular PCI window, because there's only 512M of outbound PCI
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* memory window on each IXP, while we need 1G for each of the BARs.
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*/
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static void __devinit ixp2800_pci_fixup(struct pci_dev *dev)
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{
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if (machine_is_ixdp2800()) {
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dev->resource[2].start = 0;
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dev->resource[2].end = 0;
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dev->resource[2].flags = 0;
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IXP2800, ixp2800_pci_fixup);
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static int __init ixdp2800_pci_setup(int nr, struct pci_sys_data *sys)
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{
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sys->mem_offset = 0x00000000;
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ixp2000_pci_setup(nr, sys);
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return 1;
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}
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static int __init ixdp2800_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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if (ixdp2x00_master_npu()) {
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/*
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* Root bus devices. Slave NPU is only one with interrupt.
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* Everything else, we just return -1 which is invalid.
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*/
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if(!dev->bus->self) {
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if(dev->devfn == IXDP2X00_SLAVE_NPU_DEVFN )
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return IRQ_IXDP2800_INGRESS_NPU;
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return -1;
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}
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/*
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* Bridge behind the PMC slot.
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*/
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if(dev->bus->self->devfn == IXDP2X00_PMC_DEVFN &&
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dev->bus->parent->self->devfn == IXDP2X00_P2P_DEVFN &&
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!dev->bus->parent->self->bus->parent)
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return IRQ_IXDP2800_PMC;
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/*
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* Device behind the first bridge
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*/
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if(dev->bus->self->devfn == IXDP2X00_P2P_DEVFN) {
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switch(dev->devfn) {
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case IXDP2X00_PMC_DEVFN:
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return IRQ_IXDP2800_PMC;
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case IXDP2800_MASTER_ENET_DEVFN:
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return IRQ_IXDP2800_EGRESS_ENET;
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case IXDP2800_SWITCH_FABRIC_DEVFN:
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return IRQ_IXDP2800_FABRIC;
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}
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}
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return -1;
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} else return IRQ_IXP2000_PCIB; /* Slave NIC interrupt */
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}
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static void __init ixdp2800_master_enable_slave(void)
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{
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volatile u32 *addr;
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printk(KERN_INFO "IXDP2800: enabling slave NPU\n");
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addr = (volatile u32 *)ixp2000_pci_config_addr(0,
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IXDP2X00_SLAVE_NPU_DEVFN,
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PCI_COMMAND);
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*addr |= PCI_COMMAND_MASTER;
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}
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static void __init ixdp2800_master_wait_for_slave_bus_scan(void)
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{
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volatile u32 *addr;
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printk(KERN_INFO "IXDP2800: waiting for slave to finish bus scan\n");
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addr = (volatile u32 *)ixp2000_pci_config_addr(0,
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IXDP2X00_SLAVE_NPU_DEVFN,
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PCI_COMMAND);
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while ((*addr & PCI_COMMAND_MEMORY) == 0)
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cpu_relax();
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}
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static void __init ixdp2800_slave_signal_bus_scan_completion(void)
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{
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printk(KERN_INFO "IXDP2800: bus scan done, signaling master\n");
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*IXP2000_PCI_CMDSTAT |= PCI_COMMAND_MEMORY;
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}
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static void __init ixdp2800_pci_postinit(void)
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{
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if (!ixdp2x00_master_npu()) {
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ixdp2x00_slave_pci_postinit();
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ixdp2800_slave_signal_bus_scan_completion();
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}
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}
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struct __initdata hw_pci ixdp2800_pci __initdata = {
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.nr_controllers = 1,
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.setup = ixdp2800_pci_setup,
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.preinit = ixdp2800_pci_preinit,
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.postinit = ixdp2800_pci_postinit,
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.scan = ixp2000_pci_scan_bus,
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.map_irq = ixdp2800_pci_map_irq,
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};
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int __init ixdp2800_pci_init(void)
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{
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if (machine_is_ixdp2800()) {
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struct pci_dev *dev;
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pci_common_init(&ixdp2800_pci);
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if (ixdp2x00_master_npu()) {
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dev = pci_get_bus_and_slot(1, IXDP2800_SLAVE_ENET_DEVFN);
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pci_remove_bus_device(dev);
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pci_dev_put(dev);
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ixdp2800_master_enable_slave();
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ixdp2800_master_wait_for_slave_bus_scan();
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} else {
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dev = pci_get_bus_and_slot(1, IXDP2800_MASTER_ENET_DEVFN);
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pci_remove_bus_device(dev);
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pci_dev_put(dev);
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}
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}
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return 0;
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}
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subsys_initcall(ixdp2800_pci_init);
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void __init ixdp2800_init_irq(void)
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{
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ixdp2x00_init_irq(IXDP2800_CPLD_INT_STAT, IXDP2800_CPLD_INT_MASK, IXDP2800_NR_IRQS);
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}
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MACHINE_START(IXDP2800, "Intel IXDP2800 Development Platform")
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/* Maintainer: MontaVista Software, Inc. */
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.phys_io = IXP2000_UART_PHYS_BASE,
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.io_pg_offst = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
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.boot_params = 0x00000100,
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.map_io = ixdp2x00_map_io,
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.init_irq = ixdp2800_init_irq,
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.timer = &ixdp2800_timer,
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.init_machine = ixdp2x00_init_machine,
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MACHINE_END
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