linux-sg2042/drivers/pinctrl/intel
Mika Westerberg 47c950d102 pinctrl: cherryview: Do not add all southwest and north GPIOs to IRQ domain
It turns out that for north and southwest communities, they can only
generate GPIO interrupts for lower 8 interrupts (IntSel value). The upper
part (8-15) can only generate GPEs (General Purpose Events).

Now the reason why EC events such as pressing hotkeys does not work if we
mask all the interrupts is that in order to generate either interrupts or
GPEs the INTMASK register must have that particular interrupt unmasked. In
case of GPEs the CPU does not trigger normal interrupt (and thus the GPIO
driver does not see it) but instead it causes SCI (System Control
Interrupt) to be triggered with the GPE in question set.

To make this all work as expected we only add those GPIOs to the IRQ domain
that can actually generate interrupts (IntSel value 0-7) and skip others.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-23 14:57:33 +02:00
..
Kconfig pinctrl: intel: Add Intel Merrifield pin controller support 2016-06-29 09:59:35 +02:00
Makefile pinctrl: intel: Add Intel Merrifield pin controller support 2016-06-29 09:59:35 +02:00
pinctrl-baytrail.c This is the bulk of pin control changes for the v4.8 kernel cycle. 2016-07-28 17:06:51 -07:00
pinctrl-broxton.c pinctrl/broxton: enable platform device in the absence of ACPI enumeration 2016-06-15 08:37:42 +02:00
pinctrl-cherryview.c pinctrl: cherryview: Do not add all southwest and north GPIOs to IRQ domain 2016-09-23 14:57:33 +02:00
pinctrl-intel.c pinctrl: intel: Protect set wake flow by spin lock 2016-07-11 11:15:33 +02:00
pinctrl-intel.h pinctrl: intel: fix bug of register offset calculation 2015-12-10 23:01:41 +01:00
pinctrl-merrifield.c pinctrl: intel: merrifield: Add missed header 2016-08-10 15:46:28 +02:00
pinctrl-sunrisepoint.c pinctrl: intel: fix bug of register offset calculation 2015-12-10 23:01:41 +01:00