176 lines
4.3 KiB
C
176 lines
4.3 KiB
C
/*
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* Copyright(c) 2015 EZchip Technologies.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in
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* the file called "COPYING".
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*/
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <linux/log2.h>
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#include <asm/arcregs.h>
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#include <plat/mtm.h>
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#include <plat/smp.h>
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#define MT_HS_CNT_MIN 0x01
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#define MT_HS_CNT_MAX 0xFF
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#define MT_CTRL_ST_CNT 0xF
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#define NPS_NUM_HW_THREADS 0x10
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static int mtm_hs_ctr = MT_HS_CNT_MAX;
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#ifdef CONFIG_EZNPS_MEM_ERROR_ALIGN
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int do_memory_error(unsigned long address, struct pt_regs *regs)
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{
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die("Invalid Mem Access", regs, address);
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return 1;
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}
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#endif
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static void mtm_init_nat(int cpu)
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{
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struct nps_host_reg_mtm_cfg mtm_cfg;
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struct nps_host_reg_aux_udmc udmc;
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int log_nat, nat = 0, i, t;
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/* Iterate core threads and update nat */
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for (i = 0, t = cpu; i < NPS_NUM_HW_THREADS; i++, t++)
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nat += test_bit(t, cpumask_bits(cpu_possible_mask));
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log_nat = ilog2(nat);
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udmc.value = read_aux_reg(CTOP_AUX_UDMC);
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udmc.nat = log_nat;
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write_aux_reg(CTOP_AUX_UDMC, udmc.value);
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mtm_cfg.value = ioread32be(MTM_CFG(cpu));
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mtm_cfg.nat = log_nat;
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iowrite32be(mtm_cfg.value, MTM_CFG(cpu));
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}
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static void mtm_init_thread(int cpu)
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{
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int i, tries = 5;
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struct nps_host_reg_thr_init thr_init;
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struct nps_host_reg_thr_init_sts thr_init_sts;
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/* Set thread init register */
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thr_init.value = 0;
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iowrite32be(thr_init.value, MTM_THR_INIT(cpu));
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thr_init.thr_id = NPS_CPU_TO_THREAD_NUM(cpu);
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thr_init.str = 1;
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iowrite32be(thr_init.value, MTM_THR_INIT(cpu));
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/* Poll till thread init is done */
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for (i = 0; i < tries; i++) {
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thr_init_sts.value = ioread32be(MTM_THR_INIT_STS(cpu));
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if (thr_init_sts.thr_id == thr_init.thr_id) {
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if (thr_init_sts.bsy)
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continue;
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else if (thr_init_sts.err)
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pr_warn("Failed to thread init cpu %u\n", cpu);
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break;
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}
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pr_warn("Wrong thread id in thread init for cpu %u\n", cpu);
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break;
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}
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if (i == tries)
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pr_warn("Got thread init timeout for cpu %u\n", cpu);
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}
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int mtm_enable_thread(int cpu)
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{
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struct nps_host_reg_mtm_cfg mtm_cfg;
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if (NPS_CPU_TO_THREAD_NUM(cpu) == 0)
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return 1;
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/* Enable thread in mtm */
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mtm_cfg.value = ioread32be(MTM_CFG(cpu));
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mtm_cfg.ten |= (1 << (NPS_CPU_TO_THREAD_NUM(cpu)));
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iowrite32be(mtm_cfg.value, MTM_CFG(cpu));
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return 0;
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}
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void mtm_enable_core(unsigned int cpu)
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{
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int i;
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struct nps_host_reg_aux_mt_ctrl mt_ctrl;
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struct nps_host_reg_mtm_cfg mtm_cfg;
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struct nps_host_reg_aux_dpc dpc;
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/*
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* Initializing dpc register in each CPU.
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* Overwriting the init value of the DPC
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* register so that CMEM and FMT virtual address
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* spaces are accessible, and Data Plane HW
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* facilities are enabled.
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*/
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dpc.ien = 1;
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dpc.men = 1;
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write_aux_reg(CTOP_AUX_DPC, dpc.value);
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if (NPS_CPU_TO_THREAD_NUM(cpu) != 0)
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return;
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/* Initialize Number of Active Threads */
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mtm_init_nat(cpu);
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/* Initialize mtm_cfg */
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mtm_cfg.value = ioread32be(MTM_CFG(cpu));
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mtm_cfg.ten = 1;
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iowrite32be(mtm_cfg.value, MTM_CFG(cpu));
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/* Initialize all other threads in core */
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for (i = 1; i < NPS_NUM_HW_THREADS; i++)
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mtm_init_thread(cpu + i);
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/* Enable HW schedule, stall counter, mtm */
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mt_ctrl.value = 0;
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mt_ctrl.hsen = 1;
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mt_ctrl.hs_cnt = mtm_hs_ctr;
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mt_ctrl.mten = 1;
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write_aux_reg(CTOP_AUX_MT_CTRL, mt_ctrl.value);
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/*
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* HW scheduling mechanism will start working
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* Only after call to instruction "schd.rw".
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* cpu_relax() calls "schd.rw" instruction.
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*/
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cpu_relax();
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}
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/* Verify and set the value of the mtm hs counter */
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static int __init set_mtm_hs_ctr(char *ctr_str)
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{
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long hs_ctr;
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int ret;
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ret = kstrtol(ctr_str, 0, &hs_ctr);
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if (ret || hs_ctr > MT_HS_CNT_MAX || hs_ctr < MT_HS_CNT_MIN) {
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pr_err("** Invalid @nps_mtm_hs_ctr [%d] needs to be [%d:%d] (incl)\n",
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hs_ctr, MT_HS_CNT_MIN, MT_HS_CNT_MAX);
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return -EINVAL;
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}
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mtm_hs_ctr = hs_ctr;
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return 0;
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}
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early_param("nps_mtm_hs_ctr", set_mtm_hs_ctr);
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