264 lines
6.8 KiB
C
264 lines
6.8 KiB
C
/*
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* Common Performance counter support functions for PowerISA v2.07 processors.
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*
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* Copyright 2009 Paul Mackerras, IBM Corporation.
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* Copyright 2013 Michael Ellerman, IBM Corporation.
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* Copyright 2016 Madhavan Srinivasan, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include "isa207-common.h"
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static inline bool event_is_fab_match(u64 event)
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{
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/* Only check pmc, unit and pmcxsel, ignore the edge bit (0) */
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event &= 0xff0fe;
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/* PM_MRK_FAB_RSP_MATCH & PM_MRK_FAB_RSP_MATCH_CYC */
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return (event == 0x30056 || event == 0x4f052);
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}
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int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp)
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{
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unsigned int unit, pmc, cache, ebb;
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unsigned long mask, value;
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mask = value = 0;
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if (event & ~EVENT_VALID_MASK)
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return -1;
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pmc = (event >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
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unit = (event >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK;
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cache = (event >> EVENT_CACHE_SEL_SHIFT) & EVENT_CACHE_SEL_MASK;
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ebb = (event >> EVENT_EBB_SHIFT) & EVENT_EBB_MASK;
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if (pmc) {
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u64 base_event;
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if (pmc > 6)
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return -1;
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/* Ignore Linux defined bits when checking event below */
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base_event = event & ~EVENT_LINUX_MASK;
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if (pmc >= 5 && base_event != 0x500fa &&
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base_event != 0x600f4)
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return -1;
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mask |= CNST_PMC_MASK(pmc);
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value |= CNST_PMC_VAL(pmc);
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}
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if (pmc <= 4) {
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/*
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* Add to number of counters in use. Note this includes events with
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* a PMC of 0 - they still need a PMC, it's just assigned later.
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* Don't count events on PMC 5 & 6, there is only one valid event
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* on each of those counters, and they are handled above.
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*/
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mask |= CNST_NC_MASK;
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value |= CNST_NC_VAL;
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}
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if (unit >= 6 && unit <= 9) {
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/*
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* L2/L3 events contain a cache selector field, which is
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* supposed to be programmed into MMCRC. However MMCRC is only
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* HV writable, and there is no API for guest kernels to modify
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* it. The solution is for the hypervisor to initialise the
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* field to zeroes, and for us to only ever allow events that
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* have a cache selector of zero. The bank selector (bit 3) is
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* irrelevant, as long as the rest of the value is 0.
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*/
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if (cache & 0x7)
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return -1;
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} else if (event & EVENT_IS_L1) {
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mask |= CNST_L1_QUAL_MASK;
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value |= CNST_L1_QUAL_VAL(cache);
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}
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if (event & EVENT_IS_MARKED) {
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mask |= CNST_SAMPLE_MASK;
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value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT);
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}
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/*
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* Special case for PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC,
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* the threshold control bits are used for the match value.
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*/
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if (event_is_fab_match(event)) {
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mask |= CNST_FAB_MATCH_MASK;
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value |= CNST_FAB_MATCH_VAL(event >> EVENT_THR_CTL_SHIFT);
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} else {
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/*
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* Check the mantissa upper two bits are not zero, unless the
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* exponent is also zero. See the THRESH_CMP_MANTISSA doc.
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*/
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unsigned int cmp, exp;
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cmp = (event >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK;
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exp = cmp >> 7;
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if (exp && (cmp & 0x60) == 0)
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return -1;
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mask |= CNST_THRESH_MASK;
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value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
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}
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if (!pmc && ebb)
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/* EBB events must specify the PMC */
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return -1;
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if (event & EVENT_WANTS_BHRB) {
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if (!ebb)
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/* Only EBB events can request BHRB */
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return -1;
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mask |= CNST_IFM_MASK;
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value |= CNST_IFM_VAL(event >> EVENT_IFM_SHIFT);
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}
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/*
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* All events must agree on EBB, either all request it or none.
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* EBB events are pinned & exclusive, so this should never actually
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* hit, but we leave it as a fallback in case.
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*/
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mask |= CNST_EBB_VAL(ebb);
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value |= CNST_EBB_MASK;
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*maskp = mask;
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*valp = value;
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return 0;
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}
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int isa207_compute_mmcr(u64 event[], int n_ev,
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unsigned int hwc[], unsigned long mmcr[],
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struct perf_event *pevents[])
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{
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unsigned long mmcra, mmcr1, mmcr2, unit, combine, psel, cache, val;
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unsigned int pmc, pmc_inuse;
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int i;
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pmc_inuse = 0;
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/* First pass to count resource use */
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for (i = 0; i < n_ev; ++i) {
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pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
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if (pmc)
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pmc_inuse |= 1 << pmc;
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}
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/* In continuous sampling mode, update SDAR on TLB miss */
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mmcra = MMCRA_SDAR_MODE_TLB;
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mmcr1 = mmcr2 = 0;
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/* Second pass: assign PMCs, set all MMCR1 fields */
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for (i = 0; i < n_ev; ++i) {
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pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
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unit = (event[i] >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK;
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combine = (event[i] >> EVENT_COMBINE_SHIFT) & EVENT_COMBINE_MASK;
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psel = event[i] & EVENT_PSEL_MASK;
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if (!pmc) {
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for (pmc = 1; pmc <= 4; ++pmc) {
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if (!(pmc_inuse & (1 << pmc)))
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break;
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}
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pmc_inuse |= 1 << pmc;
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}
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if (pmc <= 4) {
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mmcr1 |= unit << MMCR1_UNIT_SHIFT(pmc);
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mmcr1 |= combine << MMCR1_COMBINE_SHIFT(pmc);
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mmcr1 |= psel << MMCR1_PMCSEL_SHIFT(pmc);
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}
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if (event[i] & EVENT_IS_L1) {
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cache = event[i] >> EVENT_CACHE_SEL_SHIFT;
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mmcr1 |= (cache & 1) << MMCR1_IC_QUAL_SHIFT;
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cache >>= 1;
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mmcr1 |= (cache & 1) << MMCR1_DC_QUAL_SHIFT;
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}
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if (event[i] & EVENT_IS_MARKED) {
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mmcra |= MMCRA_SAMPLE_ENABLE;
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val = (event[i] >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK;
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if (val) {
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mmcra |= (val & 3) << MMCRA_SAMP_MODE_SHIFT;
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mmcra |= (val >> 2) << MMCRA_SAMP_ELIG_SHIFT;
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}
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}
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/*
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* PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC,
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* the threshold bits are used for the match value.
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*/
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if (event_is_fab_match(event[i])) {
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mmcr1 |= ((event[i] >> EVENT_THR_CTL_SHIFT) &
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EVENT_THR_CTL_MASK) << MMCR1_FAB_SHIFT;
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} else {
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val = (event[i] >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK;
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mmcra |= val << MMCRA_THR_CTL_SHIFT;
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val = (event[i] >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK;
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mmcra |= val << MMCRA_THR_SEL_SHIFT;
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val = (event[i] >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK;
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mmcra |= val << MMCRA_THR_CMP_SHIFT;
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}
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if (event[i] & EVENT_WANTS_BHRB) {
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val = (event[i] >> EVENT_IFM_SHIFT) & EVENT_IFM_MASK;
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mmcra |= val << MMCRA_IFM_SHIFT;
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}
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if (pevents[i]->attr.exclude_user)
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mmcr2 |= MMCR2_FCP(pmc);
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if (pevents[i]->attr.exclude_hv)
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mmcr2 |= MMCR2_FCH(pmc);
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if (pevents[i]->attr.exclude_kernel) {
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if (cpu_has_feature(CPU_FTR_HVMODE))
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mmcr2 |= MMCR2_FCH(pmc);
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else
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mmcr2 |= MMCR2_FCS(pmc);
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}
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hwc[i] = pmc - 1;
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}
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/* Return MMCRx values */
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mmcr[0] = 0;
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/* pmc_inuse is 1-based */
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if (pmc_inuse & 2)
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mmcr[0] = MMCR0_PMC1CE;
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if (pmc_inuse & 0x7c)
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mmcr[0] |= MMCR0_PMCjCE;
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/* If we're not using PMC 5 or 6, freeze them */
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if (!(pmc_inuse & 0x60))
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mmcr[0] |= MMCR0_FC56;
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mmcr[1] = mmcr1;
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mmcr[2] = mmcra;
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mmcr[3] = mmcr2;
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return 0;
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}
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void isa207_disable_pmc(unsigned int pmc, unsigned long mmcr[])
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{
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if (pmc <= 3)
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mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SHIFT(pmc + 1));
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}
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