424 lines
10 KiB
C
424 lines
10 KiB
C
/*
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* ip27-irq.c: Highlevel interrupt handling for IP27 architecture.
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*
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* Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org)
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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* Copyright (C) 1999 - 2001 Kanoj Sarcar
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*/
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#undef DEBUG
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/errno.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/timex.h>
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#include <linux/slab.h>
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#include <linux/random.h>
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#include <linux/kernel.h>
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#include <linux/kernel_stat.h>
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#include <linux/delay.h>
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#include <linux/bitops.h>
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#include <asm/bootinfo.h>
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#include <asm/io.h>
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#include <asm/mipsregs.h>
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#include <asm/system.h>
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#include <asm/processor.h>
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#include <asm/pci/bridge.h>
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#include <asm/sn/addrs.h>
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#include <asm/sn/agent.h>
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#include <asm/sn/arch.h>
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#include <asm/sn/hub.h>
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#include <asm/sn/intr.h>
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/*
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* Linux has a controller-independent x86 interrupt architecture.
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* every controller has a 'controller-template', that is used
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* by the main code to do the right thing. Each driver-visible
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* interrupt source is transparently wired to the apropriate
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* controller. Thus drivers need not be aware of the
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* interrupt-controller.
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*
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* Various interrupt controllers we handle: 8259 PIC, SMP IO-APIC,
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* PIIX4's internal 8259 PIC and SGI's Visual Workstation Cobalt (IO-)APIC.
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* (IO-APICs assumed to be messaging to Pentium local-APICs)
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*
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* the code is designed to be easily extended with new/different
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* interrupt controllers, without having to do assembly magic.
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*/
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extern asmlinkage void ip27_irq(void);
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extern struct bridge_controller *irq_to_bridge[];
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extern int irq_to_slot[];
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/*
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* use these macros to get the encoded nasid and widget id
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* from the irq value
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*/
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#define IRQ_TO_BRIDGE(i) irq_to_bridge[(i)]
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#define SLOT_FROM_PCI_IRQ(i) irq_to_slot[i]
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static inline int alloc_level(int cpu, int irq)
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{
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struct hub_data *hub = hub_data(cpu_to_node(cpu));
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struct slice_data *si = cpu_data[cpu].data;
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int level;
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level = find_first_zero_bit(hub->irq_alloc_mask, LEVELS_PER_SLICE);
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if (level >= LEVELS_PER_SLICE)
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panic("Cpu %d flooded with devices\n", cpu);
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__set_bit(level, hub->irq_alloc_mask);
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si->level_to_irq[level] = irq;
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return level;
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}
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static inline int find_level(cpuid_t *cpunum, int irq)
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{
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int cpu, i;
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for_each_online_cpu(cpu) {
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struct slice_data *si = cpu_data[cpu].data;
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for (i = BASE_PCI_IRQ; i < LEVELS_PER_SLICE; i++)
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if (si->level_to_irq[i] == irq) {
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*cpunum = cpu;
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return i;
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}
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}
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panic("Could not identify cpu/level for irq %d\n", irq);
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}
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/*
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* Find first bit set
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*/
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static int ms1bit(unsigned long x)
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{
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int b = 0, s;
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s = 16; if (x >> 16 == 0) s = 0; b += s; x >>= s;
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s = 8; if (x >> 8 == 0) s = 0; b += s; x >>= s;
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s = 4; if (x >> 4 == 0) s = 0; b += s; x >>= s;
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s = 2; if (x >> 2 == 0) s = 0; b += s; x >>= s;
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s = 1; if (x >> 1 == 0) s = 0; b += s;
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return b;
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}
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/*
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* This code is unnecessarily complex, because we do IRQF_DISABLED
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* intr enabling. Basically, once we grab the set of intrs we need
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* to service, we must mask _all_ these interrupts; firstly, to make
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* sure the same intr does not intr again, causing recursion that
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* can lead to stack overflow. Secondly, we can not just mask the
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* one intr we are do_IRQing, because the non-masked intrs in the
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* first set might intr again, causing multiple servicings of the
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* same intr. This effect is mostly seen for intercpu intrs.
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* Kanoj 05.13.00
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*/
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static void ip27_do_irq_mask0(void)
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{
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int irq, swlevel;
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hubreg_t pend0, mask0;
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cpuid_t cpu = smp_processor_id();
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int pi_int_mask0 =
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(cputoslice(cpu) == 0) ? PI_INT_MASK0_A : PI_INT_MASK0_B;
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/* copied from Irix intpend0() */
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pend0 = LOCAL_HUB_L(PI_INT_PEND0);
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mask0 = LOCAL_HUB_L(pi_int_mask0);
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pend0 &= mask0; /* Pick intrs we should look at */
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if (!pend0)
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return;
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swlevel = ms1bit(pend0);
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#ifdef CONFIG_SMP
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if (pend0 & (1UL << CPU_RESCHED_A_IRQ)) {
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LOCAL_HUB_CLR_INTR(CPU_RESCHED_A_IRQ);
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} else if (pend0 & (1UL << CPU_RESCHED_B_IRQ)) {
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LOCAL_HUB_CLR_INTR(CPU_RESCHED_B_IRQ);
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} else if (pend0 & (1UL << CPU_CALL_A_IRQ)) {
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LOCAL_HUB_CLR_INTR(CPU_CALL_A_IRQ);
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smp_call_function_interrupt();
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} else if (pend0 & (1UL << CPU_CALL_B_IRQ)) {
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LOCAL_HUB_CLR_INTR(CPU_CALL_B_IRQ);
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smp_call_function_interrupt();
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} else
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#endif
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{
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/* "map" swlevel to irq */
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struct slice_data *si = cpu_data[cpu].data;
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irq = si->level_to_irq[swlevel];
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do_IRQ(irq);
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}
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LOCAL_HUB_L(PI_INT_PEND0);
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}
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static void ip27_do_irq_mask1(void)
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{
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int irq, swlevel;
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hubreg_t pend1, mask1;
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cpuid_t cpu = smp_processor_id();
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int pi_int_mask1 = (cputoslice(cpu) == 0) ? PI_INT_MASK1_A : PI_INT_MASK1_B;
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struct slice_data *si = cpu_data[cpu].data;
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/* copied from Irix intpend0() */
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pend1 = LOCAL_HUB_L(PI_INT_PEND1);
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mask1 = LOCAL_HUB_L(pi_int_mask1);
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pend1 &= mask1; /* Pick intrs we should look at */
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if (!pend1)
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return;
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swlevel = ms1bit(pend1);
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/* "map" swlevel to irq */
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irq = si->level_to_irq[swlevel];
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LOCAL_HUB_CLR_INTR(swlevel);
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do_IRQ(irq);
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LOCAL_HUB_L(PI_INT_PEND1);
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}
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static void ip27_prof_timer(void)
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{
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panic("CPU %d got a profiling interrupt", smp_processor_id());
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}
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static void ip27_hub_error(void)
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{
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panic("CPU %d got a hub error interrupt", smp_processor_id());
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}
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static int intr_connect_level(int cpu, int bit)
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{
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nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
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struct slice_data *si = cpu_data[cpu].data;
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set_bit(bit, si->irq_enable_mask);
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if (!cputoslice(cpu)) {
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REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]);
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REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]);
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} else {
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REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]);
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REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]);
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}
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return 0;
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}
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static int intr_disconnect_level(int cpu, int bit)
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{
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nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
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struct slice_data *si = cpu_data[cpu].data;
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clear_bit(bit, si->irq_enable_mask);
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if (!cputoslice(cpu)) {
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REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]);
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REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]);
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} else {
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REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]);
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REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]);
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}
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return 0;
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}
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/* Startup one of the (PCI ...) IRQs routes over a bridge. */
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static unsigned int startup_bridge_irq(unsigned int irq)
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{
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struct bridge_controller *bc;
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bridgereg_t device;
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bridge_t *bridge;
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int pin, swlevel;
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cpuid_t cpu;
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pin = SLOT_FROM_PCI_IRQ(irq);
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bc = IRQ_TO_BRIDGE(irq);
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bridge = bc->base;
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pr_debug("bridge_startup(): irq= 0x%x pin=%d\n", irq, pin);
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/*
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* "map" irq to a swlevel greater than 6 since the first 6 bits
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* of INT_PEND0 are taken
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*/
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swlevel = find_level(&cpu, irq);
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bridge->b_int_addr[pin].addr = (0x20000 | swlevel | (bc->nasid << 8));
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bridge->b_int_enable |= (1 << pin);
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bridge->b_int_enable |= 0x7ffffe00; /* more stuff in int_enable */
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/*
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* Enable sending of an interrupt clear packt to the hub on a high to
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* low transition of the interrupt pin.
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*
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* IRIX sets additional bits in the address which are documented as
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* reserved in the bridge docs.
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*/
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bridge->b_int_mode |= (1UL << pin);
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/*
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* We assume the bridge to have a 1:1 mapping between devices
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* (slots) and intr pins.
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*/
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device = bridge->b_int_device;
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device &= ~(7 << (pin*3));
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device |= (pin << (pin*3));
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bridge->b_int_device = device;
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bridge->b_wid_tflush;
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intr_connect_level(cpu, swlevel);
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return 0; /* Never anything pending. */
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}
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/* Shutdown one of the (PCI ...) IRQs routes over a bridge. */
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static void shutdown_bridge_irq(unsigned int irq)
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{
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struct bridge_controller *bc = IRQ_TO_BRIDGE(irq);
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bridge_t *bridge = bc->base;
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int pin, swlevel;
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cpuid_t cpu;
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pr_debug("bridge_shutdown: irq 0x%x\n", irq);
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pin = SLOT_FROM_PCI_IRQ(irq);
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/*
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* map irq to a swlevel greater than 6 since the first 6 bits
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* of INT_PEND0 are taken
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*/
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swlevel = find_level(&cpu, irq);
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intr_disconnect_level(cpu, swlevel);
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bridge->b_int_enable &= ~(1 << pin);
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bridge->b_wid_tflush;
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}
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static inline void enable_bridge_irq(unsigned int irq)
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{
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cpuid_t cpu;
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int swlevel;
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swlevel = find_level(&cpu, irq); /* Criminal offence */
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intr_connect_level(cpu, swlevel);
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}
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static inline void disable_bridge_irq(unsigned int irq)
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{
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cpuid_t cpu;
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int swlevel;
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swlevel = find_level(&cpu, irq); /* Criminal offence */
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intr_disconnect_level(cpu, swlevel);
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}
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static struct irq_chip bridge_irq_type = {
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.name = "bridge",
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.startup = startup_bridge_irq,
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.shutdown = shutdown_bridge_irq,
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.ack = disable_bridge_irq,
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.mask = disable_bridge_irq,
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.mask_ack = disable_bridge_irq,
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.unmask = enable_bridge_irq,
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};
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void __devinit register_bridge_irq(unsigned int irq)
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{
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set_irq_chip_and_handler(irq, &bridge_irq_type, handle_level_irq);
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}
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int __devinit request_bridge_irq(struct bridge_controller *bc)
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{
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int irq = allocate_irqno();
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int swlevel, cpu;
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nasid_t nasid;
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if (irq < 0)
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return irq;
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/*
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* "map" irq to a swlevel greater than 6 since the first 6 bits
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* of INT_PEND0 are taken
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*/
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cpu = bc->irq_cpu;
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swlevel = alloc_level(cpu, irq);
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if (unlikely(swlevel < 0)) {
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free_irqno(irq);
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return -EAGAIN;
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}
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/* Make sure it's not already pending when we connect it. */
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nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
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REMOTE_HUB_CLR_INTR(nasid, swlevel);
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intr_connect_level(cpu, swlevel);
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register_bridge_irq(irq);
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return irq;
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned long pending = read_c0_cause() & read_c0_status();
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extern unsigned int rt_timer_irq;
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if (pending & CAUSEF_IP4)
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do_IRQ(rt_timer_irq);
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else if (pending & CAUSEF_IP2) /* PI_INT_PEND_0 or CC_PEND_{A|B} */
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ip27_do_irq_mask0();
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else if (pending & CAUSEF_IP3) /* PI_INT_PEND_1 */
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ip27_do_irq_mask1();
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else if (pending & CAUSEF_IP5)
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ip27_prof_timer();
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else if (pending & CAUSEF_IP6)
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ip27_hub_error();
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}
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void __init arch_init_irq(void)
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{
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}
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void install_ipi(void)
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{
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int slice = LOCAL_HUB_L(PI_CPU_NUM);
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int cpu = smp_processor_id();
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struct slice_data *si = cpu_data[cpu].data;
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struct hub_data *hub = hub_data(cpu_to_node(cpu));
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int resched, call;
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resched = CPU_RESCHED_A_IRQ + slice;
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__set_bit(resched, hub->irq_alloc_mask);
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__set_bit(resched, si->irq_enable_mask);
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LOCAL_HUB_CLR_INTR(resched);
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call = CPU_CALL_A_IRQ + slice;
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__set_bit(call, hub->irq_alloc_mask);
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__set_bit(call, si->irq_enable_mask);
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LOCAL_HUB_CLR_INTR(call);
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if (slice == 0) {
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LOCAL_HUB_S(PI_INT_MASK0_A, si->irq_enable_mask[0]);
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LOCAL_HUB_S(PI_INT_MASK1_A, si->irq_enable_mask[1]);
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} else {
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LOCAL_HUB_S(PI_INT_MASK0_B, si->irq_enable_mask[0]);
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LOCAL_HUB_S(PI_INT_MASK1_B, si->irq_enable_mask[1]);
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}
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}
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