864 lines
22 KiB
C
864 lines
22 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <linux/module.h>
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#include <linux/fdtable.h>
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#include <linux/uaccess.h>
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#include <drm/drmP.h>
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#include "radeon.h"
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#include "cikd.h"
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#include "cik_reg.h"
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#include "radeon_kfd.h"
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#include "radeon_ucode.h"
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#include <linux/firmware.h>
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#include "cik_structs.h"
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#define CIK_PIPE_PER_MEC (4)
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static const uint32_t watchRegs[MAX_WATCH_ADDRESSES * ADDRESS_WATCH_REG_MAX] = {
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TCP_WATCH0_ADDR_H, TCP_WATCH0_ADDR_L, TCP_WATCH0_CNTL,
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TCP_WATCH1_ADDR_H, TCP_WATCH1_ADDR_L, TCP_WATCH1_CNTL,
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TCP_WATCH2_ADDR_H, TCP_WATCH2_ADDR_L, TCP_WATCH2_CNTL,
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TCP_WATCH3_ADDR_H, TCP_WATCH3_ADDR_L, TCP_WATCH3_CNTL
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};
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struct kgd_mem {
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struct radeon_bo *bo;
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uint64_t gpu_addr;
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void *cpu_ptr;
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};
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static int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
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void **mem_obj, uint64_t *gpu_addr,
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void **cpu_ptr);
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static void free_gtt_mem(struct kgd_dev *kgd, void *mem_obj);
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static uint64_t get_vmem_size(struct kgd_dev *kgd);
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static uint64_t get_gpu_clock_counter(struct kgd_dev *kgd);
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static uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd);
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static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type);
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/*
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* Register access functions
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*/
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static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
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uint32_t sh_mem_config, uint32_t sh_mem_ape1_base,
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uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
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static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
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unsigned int vmid);
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static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
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uint32_t hpd_size, uint64_t hpd_gpu_addr);
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static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id);
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static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
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uint32_t queue_id, uint32_t __user *wptr);
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static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd);
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static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
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uint32_t pipe_id, uint32_t queue_id);
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static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
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unsigned int timeout, uint32_t pipe_id,
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uint32_t queue_id);
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static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
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static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
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unsigned int timeout);
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static int kgd_address_watch_disable(struct kgd_dev *kgd);
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static int kgd_address_watch_execute(struct kgd_dev *kgd,
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unsigned int watch_point_id,
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uint32_t cntl_val,
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uint32_t addr_hi,
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uint32_t addr_lo);
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static int kgd_wave_control_execute(struct kgd_dev *kgd,
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uint32_t gfx_index_val,
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uint32_t sq_cmd);
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static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
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unsigned int watch_point_id,
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unsigned int reg_offset);
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static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, uint8_t vmid);
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static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
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uint8_t vmid);
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static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid);
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static const struct kfd2kgd_calls kfd2kgd = {
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.init_gtt_mem_allocation = alloc_gtt_mem,
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.free_gtt_mem = free_gtt_mem,
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.get_vmem_size = get_vmem_size,
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.get_gpu_clock_counter = get_gpu_clock_counter,
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.get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
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.program_sh_mem_settings = kgd_program_sh_mem_settings,
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.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
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.init_pipeline = kgd_init_pipeline,
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.init_interrupts = kgd_init_interrupts,
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.hqd_load = kgd_hqd_load,
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.hqd_sdma_load = kgd_hqd_sdma_load,
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.hqd_is_occupied = kgd_hqd_is_occupied,
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.hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
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.hqd_destroy = kgd_hqd_destroy,
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.hqd_sdma_destroy = kgd_hqd_sdma_destroy,
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.address_watch_disable = kgd_address_watch_disable,
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.address_watch_execute = kgd_address_watch_execute,
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.wave_control_execute = kgd_wave_control_execute,
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.address_watch_get_offset = kgd_address_watch_get_offset,
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.get_atc_vmid_pasid_mapping_pasid = get_atc_vmid_pasid_mapping_pasid,
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.get_atc_vmid_pasid_mapping_valid = get_atc_vmid_pasid_mapping_valid,
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.write_vmid_invalidate_request = write_vmid_invalidate_request,
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.get_fw_version = get_fw_version
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};
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static const struct kgd2kfd_calls *kgd2kfd;
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bool radeon_kfd_init(void)
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{
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#if defined(CONFIG_HSA_AMD_MODULE)
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bool (*kgd2kfd_init_p)(unsigned, const struct kgd2kfd_calls**);
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kgd2kfd_init_p = symbol_request(kgd2kfd_init);
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if (kgd2kfd_init_p == NULL)
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return false;
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if (!kgd2kfd_init_p(KFD_INTERFACE_VERSION, &kgd2kfd)) {
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symbol_put(kgd2kfd_init);
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kgd2kfd = NULL;
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return false;
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}
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return true;
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#elif defined(CONFIG_HSA_AMD)
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if (!kgd2kfd_init(KFD_INTERFACE_VERSION, &kgd2kfd)) {
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kgd2kfd = NULL;
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return false;
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}
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return true;
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#else
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return false;
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#endif
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}
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void radeon_kfd_fini(void)
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{
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if (kgd2kfd) {
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kgd2kfd->exit();
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symbol_put(kgd2kfd_init);
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}
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}
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void radeon_kfd_device_probe(struct radeon_device *rdev)
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{
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if (kgd2kfd)
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rdev->kfd = kgd2kfd->probe((struct kgd_dev *)rdev,
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rdev->pdev, &kfd2kgd);
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}
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void radeon_kfd_device_init(struct radeon_device *rdev)
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{
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if (rdev->kfd) {
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struct kgd2kfd_shared_resources gpu_resources = {
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.compute_vmid_bitmap = 0xFF00,
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.first_compute_pipe = 1,
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.compute_pipe_count = 4 - 1,
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};
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radeon_doorbell_get_kfd_info(rdev,
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&gpu_resources.doorbell_physical_address,
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&gpu_resources.doorbell_aperture_size,
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&gpu_resources.doorbell_start_offset);
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kgd2kfd->device_init(rdev->kfd, &gpu_resources);
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}
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}
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void radeon_kfd_device_fini(struct radeon_device *rdev)
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{
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if (rdev->kfd) {
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kgd2kfd->device_exit(rdev->kfd);
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rdev->kfd = NULL;
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}
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}
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void radeon_kfd_interrupt(struct radeon_device *rdev, const void *ih_ring_entry)
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{
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if (rdev->kfd)
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kgd2kfd->interrupt(rdev->kfd, ih_ring_entry);
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}
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void radeon_kfd_suspend(struct radeon_device *rdev)
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{
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if (rdev->kfd)
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kgd2kfd->suspend(rdev->kfd);
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}
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int radeon_kfd_resume(struct radeon_device *rdev)
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{
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int r = 0;
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if (rdev->kfd)
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r = kgd2kfd->resume(rdev->kfd);
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return r;
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}
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static int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
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void **mem_obj, uint64_t *gpu_addr,
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void **cpu_ptr)
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{
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struct radeon_device *rdev = (struct radeon_device *)kgd;
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struct kgd_mem **mem = (struct kgd_mem **) mem_obj;
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int r;
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BUG_ON(kgd == NULL);
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BUG_ON(gpu_addr == NULL);
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BUG_ON(cpu_ptr == NULL);
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*mem = kmalloc(sizeof(struct kgd_mem), GFP_KERNEL);
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if ((*mem) == NULL)
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return -ENOMEM;
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r = radeon_bo_create(rdev, size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_GTT,
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RADEON_GEM_GTT_WC, NULL, NULL, &(*mem)->bo);
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if (r) {
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dev_err(rdev->dev,
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"failed to allocate BO for amdkfd (%d)\n", r);
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return r;
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}
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/* map the buffer */
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r = radeon_bo_reserve((*mem)->bo, true);
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if (r) {
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dev_err(rdev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
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goto allocate_mem_reserve_bo_failed;
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}
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r = radeon_bo_pin((*mem)->bo, RADEON_GEM_DOMAIN_GTT,
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&(*mem)->gpu_addr);
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if (r) {
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dev_err(rdev->dev, "(%d) failed to pin bo for amdkfd\n", r);
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goto allocate_mem_pin_bo_failed;
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}
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*gpu_addr = (*mem)->gpu_addr;
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r = radeon_bo_kmap((*mem)->bo, &(*mem)->cpu_ptr);
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if (r) {
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dev_err(rdev->dev,
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"(%d) failed to map bo to kernel for amdkfd\n", r);
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goto allocate_mem_kmap_bo_failed;
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}
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*cpu_ptr = (*mem)->cpu_ptr;
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radeon_bo_unreserve((*mem)->bo);
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return 0;
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allocate_mem_kmap_bo_failed:
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radeon_bo_unpin((*mem)->bo);
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allocate_mem_pin_bo_failed:
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radeon_bo_unreserve((*mem)->bo);
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allocate_mem_reserve_bo_failed:
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radeon_bo_unref(&(*mem)->bo);
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return r;
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}
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static void free_gtt_mem(struct kgd_dev *kgd, void *mem_obj)
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{
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struct kgd_mem *mem = (struct kgd_mem *) mem_obj;
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BUG_ON(mem == NULL);
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radeon_bo_reserve(mem->bo, true);
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radeon_bo_kunmap(mem->bo);
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radeon_bo_unpin(mem->bo);
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radeon_bo_unreserve(mem->bo);
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radeon_bo_unref(&(mem->bo));
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kfree(mem);
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}
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static uint64_t get_vmem_size(struct kgd_dev *kgd)
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{
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struct radeon_device *rdev = (struct radeon_device *)kgd;
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BUG_ON(kgd == NULL);
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return rdev->mc.real_vram_size;
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}
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static uint64_t get_gpu_clock_counter(struct kgd_dev *kgd)
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{
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struct radeon_device *rdev = (struct radeon_device *)kgd;
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return rdev->asic->get_gpu_clock_counter(rdev);
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}
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static uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
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{
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struct radeon_device *rdev = (struct radeon_device *)kgd;
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/* The sclk is in quantas of 10kHz */
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return rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk / 100;
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}
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static inline struct radeon_device *get_radeon_device(struct kgd_dev *kgd)
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{
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return (struct radeon_device *)kgd;
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}
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static void write_register(struct kgd_dev *kgd, uint32_t offset, uint32_t value)
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{
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struct radeon_device *rdev = get_radeon_device(kgd);
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writel(value, (void __iomem *)(rdev->rmmio + offset));
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}
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static uint32_t read_register(struct kgd_dev *kgd, uint32_t offset)
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{
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struct radeon_device *rdev = get_radeon_device(kgd);
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return readl((void __iomem *)(rdev->rmmio + offset));
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}
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static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
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uint32_t queue, uint32_t vmid)
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{
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struct radeon_device *rdev = get_radeon_device(kgd);
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uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);
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mutex_lock(&rdev->srbm_mutex);
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write_register(kgd, SRBM_GFX_CNTL, value);
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}
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static void unlock_srbm(struct kgd_dev *kgd)
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{
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struct radeon_device *rdev = get_radeon_device(kgd);
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write_register(kgd, SRBM_GFX_CNTL, 0);
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mutex_unlock(&rdev->srbm_mutex);
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}
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static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
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uint32_t queue_id)
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{
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uint32_t mec = (++pipe_id / CIK_PIPE_PER_MEC) + 1;
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uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC);
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lock_srbm(kgd, mec, pipe, queue_id, 0);
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}
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static void release_queue(struct kgd_dev *kgd)
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{
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unlock_srbm(kgd);
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}
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static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
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uint32_t sh_mem_config,
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uint32_t sh_mem_ape1_base,
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uint32_t sh_mem_ape1_limit,
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uint32_t sh_mem_bases)
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{
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lock_srbm(kgd, 0, 0, 0, vmid);
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write_register(kgd, SH_MEM_CONFIG, sh_mem_config);
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write_register(kgd, SH_MEM_APE1_BASE, sh_mem_ape1_base);
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write_register(kgd, SH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
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write_register(kgd, SH_MEM_BASES, sh_mem_bases);
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unlock_srbm(kgd);
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}
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static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
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unsigned int vmid)
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{
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/*
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* We have to assume that there is no outstanding mapping.
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* The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0
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* because a mapping is in progress or because a mapping finished and
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* the SW cleared it.
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* So the protocol is to always wait & clear.
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*/
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uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |
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ATC_VMID_PASID_MAPPING_VALID_MASK;
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write_register(kgd, ATC_VMID0_PASID_MAPPING + vmid*sizeof(uint32_t),
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pasid_mapping);
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while (!(read_register(kgd, ATC_VMID_PASID_MAPPING_UPDATE_STATUS) &
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(1U << vmid)))
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cpu_relax();
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write_register(kgd, ATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
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/* Mapping vmid to pasid also for IH block */
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write_register(kgd, IH_VMID_0_LUT + vmid * sizeof(uint32_t),
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pasid_mapping);
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return 0;
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}
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static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
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uint32_t hpd_size, uint64_t hpd_gpu_addr)
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{
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uint32_t mec = (pipe_id / CIK_PIPE_PER_MEC) + 1;
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uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC);
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lock_srbm(kgd, mec, pipe, 0, 0);
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write_register(kgd, CP_HPD_EOP_BASE_ADDR,
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lower_32_bits(hpd_gpu_addr >> 8));
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write_register(kgd, CP_HPD_EOP_BASE_ADDR_HI,
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upper_32_bits(hpd_gpu_addr >> 8));
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write_register(kgd, CP_HPD_EOP_VMID, 0);
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write_register(kgd, CP_HPD_EOP_CONTROL, hpd_size);
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unlock_srbm(kgd);
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return 0;
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}
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static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
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{
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uint32_t mec;
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uint32_t pipe;
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mec = (pipe_id / CIK_PIPE_PER_MEC) + 1;
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pipe = (pipe_id % CIK_PIPE_PER_MEC);
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|
|
|
lock_srbm(kgd, mec, pipe, 0, 0);
|
|
|
|
write_register(kgd, CPC_INT_CNTL,
|
|
TIME_STAMP_INT_ENABLE | OPCODE_ERROR_INT_ENABLE);
|
|
|
|
unlock_srbm(kgd);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static inline uint32_t get_sdma_base_addr(struct cik_sdma_rlc_registers *m)
|
|
{
|
|
uint32_t retval;
|
|
|
|
retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
|
|
m->sdma_queue_id * KFD_CIK_SDMA_QUEUE_OFFSET;
|
|
|
|
pr_debug("kfd: sdma base address: 0x%x\n", retval);
|
|
|
|
return retval;
|
|
}
|
|
|
|
static inline struct cik_mqd *get_mqd(void *mqd)
|
|
{
|
|
return (struct cik_mqd *)mqd;
|
|
}
|
|
|
|
static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd)
|
|
{
|
|
return (struct cik_sdma_rlc_registers *)mqd;
|
|
}
|
|
|
|
static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
|
|
uint32_t queue_id, uint32_t __user *wptr)
|
|
{
|
|
uint32_t wptr_shadow, is_wptr_shadow_valid;
|
|
struct cik_mqd *m;
|
|
|
|
m = get_mqd(mqd);
|
|
|
|
is_wptr_shadow_valid = !get_user(wptr_shadow, wptr);
|
|
|
|
acquire_queue(kgd, pipe_id, queue_id);
|
|
write_register(kgd, CP_MQD_BASE_ADDR, m->cp_mqd_base_addr_lo);
|
|
write_register(kgd, CP_MQD_BASE_ADDR_HI, m->cp_mqd_base_addr_hi);
|
|
write_register(kgd, CP_MQD_CONTROL, m->cp_mqd_control);
|
|
|
|
write_register(kgd, CP_HQD_PQ_BASE, m->cp_hqd_pq_base_lo);
|
|
write_register(kgd, CP_HQD_PQ_BASE_HI, m->cp_hqd_pq_base_hi);
|
|
write_register(kgd, CP_HQD_PQ_CONTROL, m->cp_hqd_pq_control);
|
|
|
|
write_register(kgd, CP_HQD_IB_CONTROL, m->cp_hqd_ib_control);
|
|
write_register(kgd, CP_HQD_IB_BASE_ADDR, m->cp_hqd_ib_base_addr_lo);
|
|
write_register(kgd, CP_HQD_IB_BASE_ADDR_HI, m->cp_hqd_ib_base_addr_hi);
|
|
|
|
write_register(kgd, CP_HQD_IB_RPTR, m->cp_hqd_ib_rptr);
|
|
|
|
write_register(kgd, CP_HQD_PERSISTENT_STATE,
|
|
m->cp_hqd_persistent_state);
|
|
write_register(kgd, CP_HQD_SEMA_CMD, m->cp_hqd_sema_cmd);
|
|
write_register(kgd, CP_HQD_MSG_TYPE, m->cp_hqd_msg_type);
|
|
|
|
write_register(kgd, CP_HQD_ATOMIC0_PREOP_LO,
|
|
m->cp_hqd_atomic0_preop_lo);
|
|
|
|
write_register(kgd, CP_HQD_ATOMIC0_PREOP_HI,
|
|
m->cp_hqd_atomic0_preop_hi);
|
|
|
|
write_register(kgd, CP_HQD_ATOMIC1_PREOP_LO,
|
|
m->cp_hqd_atomic1_preop_lo);
|
|
|
|
write_register(kgd, CP_HQD_ATOMIC1_PREOP_HI,
|
|
m->cp_hqd_atomic1_preop_hi);
|
|
|
|
write_register(kgd, CP_HQD_PQ_RPTR_REPORT_ADDR,
|
|
m->cp_hqd_pq_rptr_report_addr_lo);
|
|
|
|
write_register(kgd, CP_HQD_PQ_RPTR_REPORT_ADDR_HI,
|
|
m->cp_hqd_pq_rptr_report_addr_hi);
|
|
|
|
write_register(kgd, CP_HQD_PQ_RPTR, m->cp_hqd_pq_rptr);
|
|
|
|
write_register(kgd, CP_HQD_PQ_WPTR_POLL_ADDR,
|
|
m->cp_hqd_pq_wptr_poll_addr_lo);
|
|
|
|
write_register(kgd, CP_HQD_PQ_WPTR_POLL_ADDR_HI,
|
|
m->cp_hqd_pq_wptr_poll_addr_hi);
|
|
|
|
write_register(kgd, CP_HQD_PQ_DOORBELL_CONTROL,
|
|
m->cp_hqd_pq_doorbell_control);
|
|
|
|
write_register(kgd, CP_HQD_VMID, m->cp_hqd_vmid);
|
|
|
|
write_register(kgd, CP_HQD_QUANTUM, m->cp_hqd_quantum);
|
|
|
|
write_register(kgd, CP_HQD_PIPE_PRIORITY, m->cp_hqd_pipe_priority);
|
|
write_register(kgd, CP_HQD_QUEUE_PRIORITY, m->cp_hqd_queue_priority);
|
|
|
|
write_register(kgd, CP_HQD_IQ_RPTR, m->cp_hqd_iq_rptr);
|
|
|
|
if (is_wptr_shadow_valid)
|
|
write_register(kgd, CP_HQD_PQ_WPTR, wptr_shadow);
|
|
|
|
write_register(kgd, CP_HQD_ACTIVE, m->cp_hqd_active);
|
|
release_queue(kgd);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd)
|
|
{
|
|
struct cik_sdma_rlc_registers *m;
|
|
uint32_t sdma_base_addr;
|
|
|
|
m = get_sdma_mqd(mqd);
|
|
sdma_base_addr = get_sdma_base_addr(m);
|
|
|
|
write_register(kgd,
|
|
sdma_base_addr + SDMA0_RLC0_VIRTUAL_ADDR,
|
|
m->sdma_rlc_virtual_addr);
|
|
|
|
write_register(kgd,
|
|
sdma_base_addr + SDMA0_RLC0_RB_BASE,
|
|
m->sdma_rlc_rb_base);
|
|
|
|
write_register(kgd,
|
|
sdma_base_addr + SDMA0_RLC0_RB_BASE_HI,
|
|
m->sdma_rlc_rb_base_hi);
|
|
|
|
write_register(kgd,
|
|
sdma_base_addr + SDMA0_RLC0_RB_RPTR_ADDR_LO,
|
|
m->sdma_rlc_rb_rptr_addr_lo);
|
|
|
|
write_register(kgd,
|
|
sdma_base_addr + SDMA0_RLC0_RB_RPTR_ADDR_HI,
|
|
m->sdma_rlc_rb_rptr_addr_hi);
|
|
|
|
write_register(kgd,
|
|
sdma_base_addr + SDMA0_RLC0_DOORBELL,
|
|
m->sdma_rlc_doorbell);
|
|
|
|
write_register(kgd,
|
|
sdma_base_addr + SDMA0_RLC0_RB_CNTL,
|
|
m->sdma_rlc_rb_cntl);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
|
|
uint32_t pipe_id, uint32_t queue_id)
|
|
{
|
|
uint32_t act;
|
|
bool retval = false;
|
|
uint32_t low, high;
|
|
|
|
acquire_queue(kgd, pipe_id, queue_id);
|
|
act = read_register(kgd, CP_HQD_ACTIVE);
|
|
if (act) {
|
|
low = lower_32_bits(queue_address >> 8);
|
|
high = upper_32_bits(queue_address >> 8);
|
|
|
|
if (low == read_register(kgd, CP_HQD_PQ_BASE) &&
|
|
high == read_register(kgd, CP_HQD_PQ_BASE_HI))
|
|
retval = true;
|
|
}
|
|
release_queue(kgd);
|
|
return retval;
|
|
}
|
|
|
|
static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
|
|
{
|
|
struct cik_sdma_rlc_registers *m;
|
|
uint32_t sdma_base_addr;
|
|
uint32_t sdma_rlc_rb_cntl;
|
|
|
|
m = get_sdma_mqd(mqd);
|
|
sdma_base_addr = get_sdma_base_addr(m);
|
|
|
|
sdma_rlc_rb_cntl = read_register(kgd,
|
|
sdma_base_addr + SDMA0_RLC0_RB_CNTL);
|
|
|
|
if (sdma_rlc_rb_cntl & SDMA_RB_ENABLE)
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
|
|
unsigned int timeout, uint32_t pipe_id,
|
|
uint32_t queue_id)
|
|
{
|
|
uint32_t temp;
|
|
|
|
acquire_queue(kgd, pipe_id, queue_id);
|
|
write_register(kgd, CP_HQD_PQ_DOORBELL_CONTROL, 0);
|
|
|
|
write_register(kgd, CP_HQD_DEQUEUE_REQUEST, reset_type);
|
|
|
|
while (true) {
|
|
temp = read_register(kgd, CP_HQD_ACTIVE);
|
|
if (temp & 0x1)
|
|
break;
|
|
if (timeout == 0) {
|
|
pr_err("kfd: cp queue preemption time out (%dms)\n",
|
|
temp);
|
|
release_queue(kgd);
|
|
return -ETIME;
|
|
}
|
|
msleep(20);
|
|
timeout -= 20;
|
|
}
|
|
|
|
release_queue(kgd);
|
|
return 0;
|
|
}
|
|
|
|
static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
|
|
unsigned int timeout)
|
|
{
|
|
struct cik_sdma_rlc_registers *m;
|
|
uint32_t sdma_base_addr;
|
|
uint32_t temp;
|
|
|
|
m = get_sdma_mqd(mqd);
|
|
sdma_base_addr = get_sdma_base_addr(m);
|
|
|
|
temp = read_register(kgd, sdma_base_addr + SDMA0_RLC0_RB_CNTL);
|
|
temp = temp & ~SDMA_RB_ENABLE;
|
|
write_register(kgd, sdma_base_addr + SDMA0_RLC0_RB_CNTL, temp);
|
|
|
|
while (true) {
|
|
temp = read_register(kgd, sdma_base_addr +
|
|
SDMA0_RLC0_CONTEXT_STATUS);
|
|
if (temp & SDMA_RLC_IDLE)
|
|
break;
|
|
if (timeout == 0)
|
|
return -ETIME;
|
|
msleep(20);
|
|
timeout -= 20;
|
|
}
|
|
|
|
write_register(kgd, sdma_base_addr + SDMA0_RLC0_DOORBELL, 0);
|
|
write_register(kgd, sdma_base_addr + SDMA0_RLC0_RB_RPTR, 0);
|
|
write_register(kgd, sdma_base_addr + SDMA0_RLC0_RB_WPTR, 0);
|
|
write_register(kgd, sdma_base_addr + SDMA0_RLC0_RB_BASE, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int kgd_address_watch_disable(struct kgd_dev *kgd)
|
|
{
|
|
union TCP_WATCH_CNTL_BITS cntl;
|
|
unsigned int i;
|
|
|
|
cntl.u32All = 0;
|
|
|
|
cntl.bitfields.valid = 0;
|
|
cntl.bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK;
|
|
cntl.bitfields.atc = 1;
|
|
|
|
/* Turning off this address until we set all the registers */
|
|
for (i = 0; i < MAX_WATCH_ADDRESSES; i++)
|
|
write_register(kgd,
|
|
watchRegs[i * ADDRESS_WATCH_REG_MAX +
|
|
ADDRESS_WATCH_REG_CNTL],
|
|
cntl.u32All);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int kgd_address_watch_execute(struct kgd_dev *kgd,
|
|
unsigned int watch_point_id,
|
|
uint32_t cntl_val,
|
|
uint32_t addr_hi,
|
|
uint32_t addr_lo)
|
|
{
|
|
union TCP_WATCH_CNTL_BITS cntl;
|
|
|
|
cntl.u32All = cntl_val;
|
|
|
|
/* Turning off this watch point until we set all the registers */
|
|
cntl.bitfields.valid = 0;
|
|
write_register(kgd,
|
|
watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
|
|
ADDRESS_WATCH_REG_CNTL],
|
|
cntl.u32All);
|
|
|
|
write_register(kgd,
|
|
watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
|
|
ADDRESS_WATCH_REG_ADDR_HI],
|
|
addr_hi);
|
|
|
|
write_register(kgd,
|
|
watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
|
|
ADDRESS_WATCH_REG_ADDR_LO],
|
|
addr_lo);
|
|
|
|
/* Enable the watch point */
|
|
cntl.bitfields.valid = 1;
|
|
|
|
write_register(kgd,
|
|
watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
|
|
ADDRESS_WATCH_REG_CNTL],
|
|
cntl.u32All);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int kgd_wave_control_execute(struct kgd_dev *kgd,
|
|
uint32_t gfx_index_val,
|
|
uint32_t sq_cmd)
|
|
{
|
|
struct radeon_device *rdev = get_radeon_device(kgd);
|
|
uint32_t data;
|
|
|
|
mutex_lock(&rdev->grbm_idx_mutex);
|
|
|
|
write_register(kgd, GRBM_GFX_INDEX, gfx_index_val);
|
|
write_register(kgd, SQ_CMD, sq_cmd);
|
|
|
|
/* Restore the GRBM_GFX_INDEX register */
|
|
|
|
data = INSTANCE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
|
|
SE_BROADCAST_WRITES;
|
|
|
|
write_register(kgd, GRBM_GFX_INDEX, data);
|
|
|
|
mutex_unlock(&rdev->grbm_idx_mutex);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
|
|
unsigned int watch_point_id,
|
|
unsigned int reg_offset)
|
|
{
|
|
return watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + reg_offset];
|
|
}
|
|
|
|
static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, uint8_t vmid)
|
|
{
|
|
uint32_t reg;
|
|
struct radeon_device *rdev = (struct radeon_device *) kgd;
|
|
|
|
reg = RREG32(ATC_VMID0_PASID_MAPPING + vmid*4);
|
|
return reg & ATC_VMID_PASID_MAPPING_VALID_MASK;
|
|
}
|
|
|
|
static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
|
|
uint8_t vmid)
|
|
{
|
|
uint32_t reg;
|
|
struct radeon_device *rdev = (struct radeon_device *) kgd;
|
|
|
|
reg = RREG32(ATC_VMID0_PASID_MAPPING + vmid*4);
|
|
return reg & ATC_VMID_PASID_MAPPING_PASID_MASK;
|
|
}
|
|
|
|
static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid)
|
|
{
|
|
struct radeon_device *rdev = (struct radeon_device *) kgd;
|
|
|
|
return WREG32(VM_INVALIDATE_REQUEST, 1 << vmid);
|
|
}
|
|
|
|
static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
|
|
{
|
|
struct radeon_device *rdev = (struct radeon_device *) kgd;
|
|
const union radeon_firmware_header *hdr;
|
|
|
|
BUG_ON(kgd == NULL || rdev->mec_fw == NULL);
|
|
|
|
switch (type) {
|
|
case KGD_ENGINE_PFP:
|
|
hdr = (const union radeon_firmware_header *) rdev->pfp_fw->data;
|
|
break;
|
|
|
|
case KGD_ENGINE_ME:
|
|
hdr = (const union radeon_firmware_header *) rdev->me_fw->data;
|
|
break;
|
|
|
|
case KGD_ENGINE_CE:
|
|
hdr = (const union radeon_firmware_header *) rdev->ce_fw->data;
|
|
break;
|
|
|
|
case KGD_ENGINE_MEC1:
|
|
hdr = (const union radeon_firmware_header *) rdev->mec_fw->data;
|
|
break;
|
|
|
|
case KGD_ENGINE_MEC2:
|
|
hdr = (const union radeon_firmware_header *)
|
|
rdev->mec2_fw->data;
|
|
break;
|
|
|
|
case KGD_ENGINE_RLC:
|
|
hdr = (const union radeon_firmware_header *) rdev->rlc_fw->data;
|
|
break;
|
|
|
|
case KGD_ENGINE_SDMA1:
|
|
case KGD_ENGINE_SDMA2:
|
|
hdr = (const union radeon_firmware_header *)
|
|
rdev->sdma_fw->data;
|
|
break;
|
|
|
|
default:
|
|
return 0;
|
|
}
|
|
|
|
if (hdr == NULL)
|
|
return 0;
|
|
|
|
/* Only 12 bit in use*/
|
|
return hdr->common.ucode_version;
|
|
}
|