517 lines
12 KiB
C
517 lines
12 KiB
C
/*
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* SS1000/SC2000 interrupt handling.
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*
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* Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
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* Heavily based on arch/sparc/kernel/irq.c.
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*/
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#include <linux/kernel_stat.h>
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#include <linux/seq_file.h>
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#include <asm/timer.h>
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#include <asm/traps.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/sbi.h>
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#include <asm/cacheflush.h>
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#include <asm/setup.h>
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#include <asm/oplib.h>
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#include "kernel.h"
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#include "irq.h"
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/* Sun4d interrupts fall roughly into two categories. SBUS and
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* cpu local. CPU local interrupts cover the timer interrupts
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* and whatnot, and we encode those as normal PILs between
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* 0 and 15.
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* SBUS interrupts are encodes as a combination of board, level and slot.
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*/
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struct sun4d_handler_data {
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unsigned int cpuid; /* target cpu */
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unsigned int real_irq; /* interrupt level */
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};
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static unsigned int sun4d_encode_irq(int board, int lvl, int slot)
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{
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return (board + 1) << 5 | (lvl << 2) | slot;
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}
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struct sun4d_timer_regs {
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u32 l10_timer_limit;
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u32 l10_cur_countx;
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u32 l10_limit_noclear;
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u32 ctrl;
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u32 l10_cur_count;
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};
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static struct sun4d_timer_regs __iomem *sun4d_timers;
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#define SUN4D_TIMER_IRQ 10
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/* Specify which cpu handle interrupts from which board.
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* Index is board - value is cpu.
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*/
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static unsigned char board_to_cpu[32];
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static int pil_to_sbus[] = {
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0,
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0,
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1,
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2,
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0,
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3,
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0,
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4,
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0,
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5,
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0,
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6,
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0,
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7,
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0,
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0,
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};
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/* Exported for sun4d_smp.c */
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DEFINE_SPINLOCK(sun4d_imsk_lock);
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/* SBUS interrupts are encoded integers including the board number
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* (plus one), the SBUS level, and the SBUS slot number. Sun4D
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* IRQ dispatch is done by:
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*
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* 1) Reading the BW local interrupt table in order to get the bus
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* interrupt mask.
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*
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* This table is indexed by SBUS interrupt level which can be
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* derived from the PIL we got interrupted on.
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*
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* 2) For each bus showing interrupt pending from #1, read the
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* SBI interrupt state register. This will indicate which slots
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* have interrupts pending for that SBUS interrupt level.
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*
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* 3) Call the genreric IRQ support.
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*/
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static void sun4d_sbus_handler_irq(int sbusl)
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{
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unsigned int bus_mask;
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unsigned int sbino, slot;
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unsigned int sbil;
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bus_mask = bw_get_intr_mask(sbusl) & 0x3ffff;
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bw_clear_intr_mask(sbusl, bus_mask);
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sbil = (sbusl << 2);
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/* Loop for each pending SBI */
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for (sbino = 0; bus_mask; sbino++, bus_mask >>= 1) {
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unsigned int idx, mask;
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if (!(bus_mask & 1))
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continue;
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/* XXX This seems to ACK the irq twice. acquire_sbi()
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* XXX uses swap, therefore this writes 0xf << sbil,
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* XXX then later release_sbi() will write the individual
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* XXX bits which were set again.
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*/
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mask = acquire_sbi(SBI2DEVID(sbino), 0xf << sbil);
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mask &= (0xf << sbil);
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/* Loop for each pending SBI slot */
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slot = (1 << sbil);
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for (idx = 0; mask != 0; idx++, slot <<= 1) {
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unsigned int pil;
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struct irq_bucket *p;
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if (!(mask & slot))
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continue;
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mask &= ~slot;
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pil = sun4d_encode_irq(sbino, sbusl, idx);
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p = irq_map[pil];
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while (p) {
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struct irq_bucket *next;
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next = p->next;
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generic_handle_irq(p->irq);
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p = next;
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}
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release_sbi(SBI2DEVID(sbino), slot);
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}
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}
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}
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void sun4d_handler_irq(int pil, struct pt_regs *regs)
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{
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struct pt_regs *old_regs;
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/* SBUS IRQ level (1 - 7) */
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int sbusl = pil_to_sbus[pil];
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/* FIXME: Is this necessary?? */
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cc_get_ipen();
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cc_set_iclr(1 << pil);
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#ifdef CONFIG_SMP
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/*
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* Check IPI data structures after IRQ has been cleared. Hard and Soft
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* IRQ can happen at the same time, so both cases are always handled.
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*/
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if (pil == SUN4D_IPI_IRQ)
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sun4d_ipi_interrupt();
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#endif
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old_regs = set_irq_regs(regs);
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irq_enter();
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if (sbusl == 0) {
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/* cpu interrupt */
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struct irq_bucket *p;
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p = irq_map[pil];
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while (p) {
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struct irq_bucket *next;
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next = p->next;
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generic_handle_irq(p->irq);
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p = next;
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}
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} else {
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/* SBUS interrupt */
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sun4d_sbus_handler_irq(sbusl);
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}
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irq_exit();
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set_irq_regs(old_regs);
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}
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static void sun4d_mask_irq(struct irq_data *data)
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{
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struct sun4d_handler_data *handler_data = data->handler_data;
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unsigned int real_irq;
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#ifdef CONFIG_SMP
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int cpuid = handler_data->cpuid;
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unsigned long flags;
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#endif
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real_irq = handler_data->real_irq;
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#ifdef CONFIG_SMP
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spin_lock_irqsave(&sun4d_imsk_lock, flags);
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cc_set_imsk_other(cpuid, cc_get_imsk_other(cpuid) | (1 << real_irq));
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spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
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#else
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cc_set_imsk(cc_get_imsk() | (1 << real_irq));
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#endif
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}
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static void sun4d_unmask_irq(struct irq_data *data)
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{
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struct sun4d_handler_data *handler_data = data->handler_data;
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unsigned int real_irq;
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#ifdef CONFIG_SMP
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int cpuid = handler_data->cpuid;
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unsigned long flags;
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#endif
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real_irq = handler_data->real_irq;
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#ifdef CONFIG_SMP
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spin_lock_irqsave(&sun4d_imsk_lock, flags);
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cc_set_imsk_other(cpuid, cc_get_imsk_other(cpuid) & ~(1 << real_irq));
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spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
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#else
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cc_set_imsk(cc_get_imsk() & ~(1 << real_irq));
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#endif
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}
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static unsigned int sun4d_startup_irq(struct irq_data *data)
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{
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irq_link(data->irq);
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sun4d_unmask_irq(data);
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return 0;
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}
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static void sun4d_shutdown_irq(struct irq_data *data)
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{
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sun4d_mask_irq(data);
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irq_unlink(data->irq);
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}
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struct irq_chip sun4d_irq = {
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.name = "sun4d",
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.irq_startup = sun4d_startup_irq,
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.irq_shutdown = sun4d_shutdown_irq,
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.irq_unmask = sun4d_unmask_irq,
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.irq_mask = sun4d_mask_irq,
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};
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#ifdef CONFIG_SMP
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/* Setup IRQ distribution scheme. */
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void __init sun4d_distribute_irqs(void)
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{
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struct device_node *dp;
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int cpuid = cpu_logical_map(1);
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if (cpuid == -1)
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cpuid = cpu_logical_map(0);
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for_each_node_by_name(dp, "sbi") {
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int devid = of_getintprop_default(dp, "device-id", 0);
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int board = of_getintprop_default(dp, "board#", 0);
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board_to_cpu[board] = cpuid;
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set_sbi_tid(devid, cpuid << 3);
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}
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printk(KERN_ERR "All sbus IRQs directed to CPU%d\n", cpuid);
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}
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#endif
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static void sun4d_clear_clock_irq(void)
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{
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sbus_readl(&sun4d_timers->l10_timer_limit);
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}
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static void sun4d_load_profile_irq(int cpu, unsigned int limit)
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{
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unsigned int value = limit ? timer_value(limit) : 0;
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bw_set_prof_limit(cpu, value);
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}
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static void __init sun4d_load_profile_irqs(void)
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{
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int cpu = 0, mid;
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while (!cpu_find_by_instance(cpu, NULL, &mid)) {
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sun4d_load_profile_irq(mid >> 3, 0);
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cpu++;
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}
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}
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unsigned int _sun4d_build_device_irq(unsigned int real_irq,
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unsigned int pil,
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unsigned int board)
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{
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struct sun4d_handler_data *handler_data;
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unsigned int irq;
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irq = irq_alloc(real_irq, pil);
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if (irq == 0) {
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prom_printf("IRQ: allocate for %d %d %d failed\n",
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real_irq, pil, board);
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goto err_out;
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}
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handler_data = irq_get_handler_data(irq);
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if (unlikely(handler_data))
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goto err_out;
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handler_data = kzalloc(sizeof(struct sun4d_handler_data), GFP_ATOMIC);
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if (unlikely(!handler_data)) {
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prom_printf("IRQ: kzalloc(sun4d_handler_data) failed.\n");
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prom_halt();
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}
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handler_data->cpuid = board_to_cpu[board];
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handler_data->real_irq = real_irq;
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irq_set_chip_and_handler_name(irq, &sun4d_irq,
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handle_level_irq, "level");
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irq_set_handler_data(irq, handler_data);
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err_out:
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return irq;
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}
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unsigned int sun4d_build_device_irq(struct platform_device *op,
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unsigned int real_irq)
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{
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struct device_node *dp = op->dev.of_node;
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struct device_node *board_parent, *bus = dp->parent;
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char *bus_connection;
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const struct linux_prom_registers *regs;
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unsigned int pil;
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unsigned int irq;
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int board, slot;
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int sbusl;
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irq = real_irq;
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while (bus) {
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if (!strcmp(bus->name, "sbi")) {
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bus_connection = "io-unit";
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break;
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}
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if (!strcmp(bus->name, "bootbus")) {
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bus_connection = "cpu-unit";
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break;
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}
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bus = bus->parent;
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}
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if (!bus)
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goto err_out;
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regs = of_get_property(dp, "reg", NULL);
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if (!regs)
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goto err_out;
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slot = regs->which_io;
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/*
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* If Bus nodes parent is not io-unit/cpu-unit or the io-unit/cpu-unit
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* lacks a "board#" property, something is very wrong.
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*/
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if (!bus->parent || strcmp(bus->parent->name, bus_connection)) {
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printk(KERN_ERR "%s: Error, parent is not %s.\n",
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bus->full_name, bus_connection);
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goto err_out;
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}
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board_parent = bus->parent;
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board = of_getintprop_default(board_parent, "board#", -1);
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if (board == -1) {
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printk(KERN_ERR "%s: Error, lacks board# property.\n",
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board_parent->full_name);
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goto err_out;
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}
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sbusl = pil_to_sbus[real_irq];
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if (sbusl)
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pil = sun4d_encode_irq(board, sbusl, slot);
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else
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pil = real_irq;
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irq = _sun4d_build_device_irq(real_irq, pil, board);
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err_out:
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return irq;
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}
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unsigned int sun4d_build_timer_irq(unsigned int board, unsigned int real_irq)
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{
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return _sun4d_build_device_irq(real_irq, real_irq, board);
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}
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static void __init sun4d_fixup_trap_table(void)
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{
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#ifdef CONFIG_SMP
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unsigned long flags;
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struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)];
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/* Adjust so that we jump directly to smp4d_ticker */
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lvl14_save[2] += smp4d_ticker - real_irq_entry;
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/* For SMP we use the level 14 ticker, however the bootup code
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* has copied the firmware's level 14 vector into the boot cpu's
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* trap table, we must fix this now or we get squashed.
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*/
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local_irq_save(flags);
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patchme_maybe_smp_msg[0] = 0x01000000; /* NOP out the branch */
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trap_table->inst_one = lvl14_save[0];
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trap_table->inst_two = lvl14_save[1];
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trap_table->inst_three = lvl14_save[2];
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trap_table->inst_four = lvl14_save[3];
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local_ops->cache_all();
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local_irq_restore(flags);
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#endif
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}
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static void __init sun4d_init_timers(void)
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{
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struct device_node *dp;
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struct resource res;
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unsigned int irq;
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const u32 *reg;
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int err;
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int board;
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dp = of_find_node_by_name(NULL, "cpu-unit");
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if (!dp) {
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prom_printf("sun4d_init_timers: Unable to find cpu-unit\n");
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prom_halt();
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}
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/* Which cpu-unit we use is arbitrary, we can view the bootbus timer
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* registers via any cpu's mapping. The first 'reg' property is the
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* bootbus.
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*/
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reg = of_get_property(dp, "reg", NULL);
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if (!reg) {
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prom_printf("sun4d_init_timers: No reg property\n");
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prom_halt();
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}
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board = of_getintprop_default(dp, "board#", -1);
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if (board == -1) {
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prom_printf("sun4d_init_timers: No board# property on cpu-unit\n");
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prom_halt();
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}
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of_node_put(dp);
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res.start = reg[1];
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res.end = reg[2] - 1;
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res.flags = reg[0] & 0xff;
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sun4d_timers = of_ioremap(&res, BW_TIMER_LIMIT,
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sizeof(struct sun4d_timer_regs), "user timer");
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if (!sun4d_timers) {
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prom_printf("sun4d_init_timers: Can't map timer regs\n");
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prom_halt();
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}
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#ifdef CONFIG_SMP
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sparc_config.cs_period = SBUS_CLOCK_RATE * 2; /* 2 seconds */
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#else
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sparc_config.cs_period = SBUS_CLOCK_RATE / HZ; /* 1/HZ sec */
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sparc_config.features |= FEAT_L10_CLOCKEVENT;
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#endif
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sparc_config.features |= FEAT_L10_CLOCKSOURCE;
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sbus_writel(timer_value(sparc_config.cs_period),
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&sun4d_timers->l10_timer_limit);
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master_l10_counter = &sun4d_timers->l10_cur_count;
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irq = sun4d_build_timer_irq(board, SUN4D_TIMER_IRQ);
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err = request_irq(irq, timer_interrupt, IRQF_TIMER, "timer", NULL);
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if (err) {
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prom_printf("sun4d_init_timers: request_irq() failed with %d\n",
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err);
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prom_halt();
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}
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sun4d_load_profile_irqs();
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sun4d_fixup_trap_table();
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}
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void __init sun4d_init_sbi_irq(void)
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{
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struct device_node *dp;
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int target_cpu;
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target_cpu = boot_cpu_id;
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for_each_node_by_name(dp, "sbi") {
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int devid = of_getintprop_default(dp, "device-id", 0);
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int board = of_getintprop_default(dp, "board#", 0);
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unsigned int mask;
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set_sbi_tid(devid, target_cpu << 3);
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board_to_cpu[board] = target_cpu;
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/* Get rid of pending irqs from PROM */
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mask = acquire_sbi(devid, 0xffffffff);
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if (mask) {
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printk(KERN_ERR "Clearing pending IRQs %08x on SBI %d\n",
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mask, board);
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release_sbi(devid, mask);
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}
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}
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}
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void __init sun4d_init_IRQ(void)
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{
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local_irq_disable();
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sparc_config.init_timers = sun4d_init_timers;
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sparc_config.build_device_irq = sun4d_build_device_irq;
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sparc_config.clock_rate = SBUS_CLOCK_RATE;
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sparc_config.clear_clock_irq = sun4d_clear_clock_irq;
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sparc_config.load_profile_irq = sun4d_load_profile_irq;
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/* Cannot enable interrupts until OBP ticker is disabled. */
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}
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