189 lines
5.5 KiB
C
189 lines
5.5 KiB
C
/* linux/include/asm-arm/arch-msm/hsusb.h
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*
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* Copyright (C) 2008 Google, Inc.
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* Author: Brian Swetland <swetland@google.com>
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* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __ASM_ARCH_MSM_HSUSB_H
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#define __ASM_ARCH_MSM_HSUSB_H
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#include <linux/types.h>
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#include <linux/usb/otg.h>
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#include <linux/clk.h>
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/**
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* Supported USB modes
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*
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* USB_PERIPHERAL Only peripheral mode is supported.
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* USB_HOST Only host mode is supported.
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* USB_OTG OTG mode is supported.
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*
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*/
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enum usb_mode_type {
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USB_NONE = 0,
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USB_PERIPHERAL,
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USB_HOST,
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USB_OTG,
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};
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/**
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* OTG control
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*
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* OTG_NO_CONTROL Id/VBUS notifications not required. Useful in host
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* only configuration.
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* OTG_PHY_CONTROL Id/VBUS notifications comes form USB PHY.
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* OTG_PMIC_CONTROL Id/VBUS notifications comes from PMIC hardware.
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* OTG_USER_CONTROL Id/VBUS notifcations comes from User via sysfs.
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*
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*/
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enum otg_control_type {
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OTG_NO_CONTROL = 0,
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OTG_PHY_CONTROL,
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OTG_PMIC_CONTROL,
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OTG_USER_CONTROL,
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};
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/**
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* PHY used in
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*
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* INVALID_PHY Unsupported PHY
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* CI_45NM_INTEGRATED_PHY Chipidea 45nm integrated PHY
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* SNPS_28NM_INTEGRATED_PHY Synopsis 28nm integrated PHY
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*
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*/
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enum msm_usb_phy_type {
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INVALID_PHY = 0,
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CI_45NM_INTEGRATED_PHY,
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SNPS_28NM_INTEGRATED_PHY,
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};
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#define IDEV_CHG_MAX 1500
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#define IUNIT 100
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/**
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* Different states involved in USB charger detection.
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*
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* USB_CHG_STATE_UNDEFINED USB charger is not connected or detection
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* process is not yet started.
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* USB_CHG_STATE_WAIT_FOR_DCD Waiting for Data pins contact.
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* USB_CHG_STATE_DCD_DONE Data pin contact is detected.
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* USB_CHG_STATE_PRIMARY_DONE Primary detection is completed (Detects
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* between SDP and DCP/CDP).
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* USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects
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* between DCP and CDP).
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* USB_CHG_STATE_DETECTED USB charger type is determined.
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*
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*/
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enum usb_chg_state {
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USB_CHG_STATE_UNDEFINED = 0,
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USB_CHG_STATE_WAIT_FOR_DCD,
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USB_CHG_STATE_DCD_DONE,
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USB_CHG_STATE_PRIMARY_DONE,
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USB_CHG_STATE_SECONDARY_DONE,
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USB_CHG_STATE_DETECTED,
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};
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/**
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* USB charger types
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*
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* USB_INVALID_CHARGER Invalid USB charger.
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* USB_SDP_CHARGER Standard downstream port. Refers to a downstream port
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* on USB2.0 compliant host/hub.
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* USB_DCP_CHARGER Dedicated charger port (AC charger/ Wall charger).
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* USB_CDP_CHARGER Charging downstream port. Enumeration can happen and
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* IDEV_CHG_MAX can be drawn irrespective of USB state.
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*
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*/
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enum usb_chg_type {
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USB_INVALID_CHARGER = 0,
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USB_SDP_CHARGER,
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USB_DCP_CHARGER,
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USB_CDP_CHARGER,
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};
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/**
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* struct msm_otg_platform_data - platform device data
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* for msm_otg driver.
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* @phy_init_seq: PHY configuration sequence. val, reg pairs
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* terminated by -1.
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* @vbus_power: VBUS power on/off routine.
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* @power_budget: VBUS power budget in mA (0 will be treated as 500mA).
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* @mode: Supported mode (OTG/peripheral/host).
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* @otg_control: OTG switch controlled by user/Id pin
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* @default_mode: Default operational mode. Applicable only if
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* OTG switch is controller by user.
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* @pclk_src_name: pclk is derived from ebi1_usb_clk in case of 7x27 and 8k
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* dfab_usb_hs_clk in case of 8660 and 8960.
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*/
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struct msm_otg_platform_data {
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int *phy_init_seq;
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void (*vbus_power)(bool on);
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unsigned power_budget;
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enum usb_mode_type mode;
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enum otg_control_type otg_control;
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enum usb_mode_type default_mode;
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enum msm_usb_phy_type phy_type;
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void (*setup_gpio)(enum usb_otg_state state);
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char *pclk_src_name;
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int (*link_clk_reset)(struct clk *link_clk, bool assert);
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int (*phy_clk_reset)(struct clk *phy_clk);
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};
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/**
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* struct msm_otg: OTG driver data. Shared by HCD and DCD.
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* @otg: USB OTG Transceiver structure.
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* @pdata: otg device platform data.
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* @irq: IRQ number assigned for HSUSB controller.
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* @clk: clock struct of usb_hs_clk.
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* @pclk: clock struct of usb_hs_pclk.
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* @pclk_src: pclk source for voting.
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* @phy_reset_clk: clock struct of usb_phy_clk.
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* @core_clk: clock struct of usb_hs_core_clk.
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* @regs: ioremapped register base address.
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* @inputs: OTG state machine inputs(Id, SessValid etc).
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* @sm_work: OTG state machine work.
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* @in_lpm: indicates low power mode (LPM) state.
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* @async_int: Async interrupt arrived.
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* @cur_power: The amount of mA available from downstream port.
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* @chg_work: Charger detection work.
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* @chg_state: The state of charger detection process.
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* @chg_type: The type of charger attached.
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* @dcd_retires: The retry count used to track Data contact
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* detection process.
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*/
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struct msm_otg {
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struct usb_phy phy;
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struct msm_otg_platform_data *pdata;
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int irq;
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struct clk *clk;
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struct clk *pclk;
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struct clk *pclk_src;
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struct clk *phy_reset_clk;
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struct clk *core_clk;
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void __iomem *regs;
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#define ID 0
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#define B_SESS_VLD 1
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unsigned long inputs;
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struct work_struct sm_work;
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atomic_t in_lpm;
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int async_int;
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unsigned cur_power;
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struct delayed_work chg_work;
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enum usb_chg_state chg_state;
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enum usb_chg_type chg_type;
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u8 dcd_retries;
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};
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#endif
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