158 lines
4.7 KiB
C
158 lines
4.7 KiB
C
/* $Id: irq.h,v 1.21 2002/01/23 11:27:36 davem Exp $
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* irq.h: IRQ registers on the 64-bit Sparc.
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*
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* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
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*/
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#ifndef _SPARC64_IRQ_H
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#define _SPARC64_IRQ_H
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#include <linux/config.h>
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#include <linux/linkage.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <asm/pil.h>
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#include <asm/ptrace.h>
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/* You should not mess with this directly. That's the job of irq.c.
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*
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* If you make changes here, please update hand coded assembler of
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* SBUS/floppy interrupt handler in entry.S -DaveM
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*
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* This is currently one DCACHE line, two buckets per L2 cache
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* line. Keep this in mind please.
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*/
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struct ino_bucket {
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/* Next handler in per-CPU PIL worklist. We know that
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* bucket pointers have the high 32-bits clear, so to
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* save space we only store the bits we need.
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*/
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/*0x00*/unsigned int irq_chain;
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/* PIL to schedule this IVEC at. */
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/*0x04*/unsigned char pil;
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/* If an IVEC arrives while irq_info is NULL, we
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* set this to notify request_irq() about the event.
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*/
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/*0x05*/unsigned char pending;
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/* Miscellaneous flags. */
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/*0x06*/unsigned char flags;
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/* This is used to deal with IBF_DMA_SYNC on
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* Sabre systems.
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*/
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/*0x07*/unsigned char synctab_ent;
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/* Reference to handler for this IRQ. If this is
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* non-NULL this means it is active and should be
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* serviced. Else the pending member is set to one
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* and later registry of the interrupt checks for
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* this condition.
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*
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* Normally this is just an irq_action structure.
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* But, on PCI, if multiple interrupt sources behind
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* a bridge have multiple interrupt sources that share
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* the same INO bucket, this points to an array of
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* pointers to four IRQ action structures.
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*/
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/*0x08*/void *irq_info;
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/* Sun5 Interrupt Clear Register. */
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/*0x10*/unsigned long iclr;
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/* Sun5 Interrupt Mapping Register. */
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/*0x18*/unsigned long imap;
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};
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#ifdef CONFIG_PCI
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extern unsigned long pci_dma_wsync;
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extern unsigned long dma_sync_reg_table[256];
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extern unsigned char dma_sync_reg_table_entry;
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#endif
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/* IMAP/ICLR register defines */
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#define IMAP_VALID 0x80000000 /* IRQ Enabled */
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#define IMAP_TID_UPA 0x7c000000 /* UPA TargetID */
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#define IMAP_TID_JBUS 0x7c000000 /* JBUS TargetID */
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#define IMAP_AID_SAFARI 0x7c000000 /* Safari AgentID */
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#define IMAP_NID_SAFARI 0x03e00000 /* Safari NodeID */
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#define IMAP_IGN 0x000007c0 /* IRQ Group Number */
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#define IMAP_INO 0x0000003f /* IRQ Number */
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#define IMAP_INR 0x000007ff /* Full interrupt number*/
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#define ICLR_IDLE 0x00000000 /* Idle state */
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#define ICLR_TRANSMIT 0x00000001 /* Transmit state */
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#define ICLR_PENDING 0x00000003 /* Pending state */
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/* Only 8-bits are available, be careful. -DaveM */
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#define IBF_DMA_SYNC 0x01 /* DMA synchronization behind PCI bridge needed. */
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#define IBF_PCI 0x02 /* Indicates PSYCHO/SABRE/SCHIZO PCI interrupt. */
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#define IBF_ACTIVE 0x04 /* This interrupt is active and has a handler. */
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#define IBF_MULTI 0x08 /* On PCI, indicates shared bucket. */
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#define IBF_INPROGRESS 0x10 /* IRQ is being serviced. */
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#define NUM_IVECS (IMAP_INR + 1)
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extern struct ino_bucket ivector_table[NUM_IVECS];
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#define __irq_ino(irq) \
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(((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0])
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#define __irq_pil(irq) ((struct ino_bucket *)(unsigned long)(irq))->pil
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#define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq))
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#define __irq(bucket) ((unsigned int)(unsigned long)(bucket))
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static __inline__ char *__irq_itoa(unsigned int irq)
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{
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static char buff[16];
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sprintf(buff, "%d,%x", __irq_pil(irq), (unsigned int)__irq_ino(irq));
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return buff;
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}
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#define NR_IRQS 16
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#define irq_canonicalize(irq) (irq)
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extern void disable_irq(unsigned int);
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#define disable_irq_nosync disable_irq
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extern void enable_irq(unsigned int);
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extern unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap);
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extern unsigned int sbus_build_irq(void *sbus, unsigned int ino);
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extern int request_fast_irq(unsigned int irq,
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irqreturn_t (*handler)(int, void *, struct pt_regs *),
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unsigned long flags, __const__ char *devname,
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void *dev_id);
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static __inline__ void set_softint(unsigned long bits)
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{
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__asm__ __volatile__("wr %0, 0x0, %%set_softint"
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: /* No outputs */
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: "r" (bits));
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}
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static __inline__ void clear_softint(unsigned long bits)
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{
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__asm__ __volatile__("wr %0, 0x0, %%clear_softint"
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: /* No outputs */
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: "r" (bits));
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}
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static __inline__ unsigned long get_softint(void)
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{
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unsigned long retval;
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__asm__ __volatile__("rd %%softint, %0"
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: "=r" (retval));
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return retval;
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}
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struct irqaction;
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struct pt_regs;
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int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
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#endif
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