362 lines
9.1 KiB
C
362 lines
9.1 KiB
C
/*
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* ULI M1575 setup code - specific to Freescale boards
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*
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* Copyright 2007 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/mc146818rtc.h>
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#include <asm/pci-bridge.h>
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#define ULI_PIRQA 0x08
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#define ULI_PIRQB 0x09
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#define ULI_PIRQC 0x0a
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#define ULI_PIRQD 0x0b
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#define ULI_PIRQE 0x0c
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#define ULI_PIRQF 0x0d
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#define ULI_PIRQG 0x0e
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#define ULI_8259_NONE 0x00
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#define ULI_8259_IRQ1 0x08
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#define ULI_8259_IRQ3 0x02
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#define ULI_8259_IRQ4 0x04
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#define ULI_8259_IRQ5 0x05
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#define ULI_8259_IRQ6 0x07
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#define ULI_8259_IRQ7 0x06
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#define ULI_8259_IRQ9 0x01
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#define ULI_8259_IRQ10 0x03
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#define ULI_8259_IRQ11 0x09
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#define ULI_8259_IRQ12 0x0b
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#define ULI_8259_IRQ14 0x0d
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#define ULI_8259_IRQ15 0x0f
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u8 uli_pirq_to_irq[8] = {
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ULI_8259_IRQ9, /* PIRQA */
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ULI_8259_IRQ10, /* PIRQB */
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ULI_8259_IRQ11, /* PIRQC */
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ULI_8259_IRQ12, /* PIRQD */
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ULI_8259_IRQ5, /* PIRQE */
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ULI_8259_IRQ6, /* PIRQF */
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ULI_8259_IRQ7, /* PIRQG */
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ULI_8259_NONE, /* PIRQH */
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};
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static inline bool is_quirk_valid(void)
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{
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return (machine_is(mpc86xx_hpcn) ||
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machine_is(mpc8544_ds) ||
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machine_is(p2020_ds) ||
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machine_is(mpc8572_ds));
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}
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/* Bridge */
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static void early_uli5249(struct pci_dev *dev)
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{
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unsigned char temp;
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if (!is_quirk_valid())
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return;
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pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO |
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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/* read/write lock */
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pci_read_config_byte(dev, 0x7c, &temp);
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pci_write_config_byte(dev, 0x7c, 0x80);
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/* set as P2P bridge */
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pci_write_config_byte(dev, PCI_CLASS_PROG, 0x01);
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dev->class |= 0x1;
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/* restore lock */
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pci_write_config_byte(dev, 0x7c, temp);
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}
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static void quirk_uli1575(struct pci_dev *dev)
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{
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int i;
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if (!is_quirk_valid())
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return;
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/*
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* ULI1575 interrupts route setup
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*/
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/* ULI1575 IRQ mapping conf register maps PIRQx to IRQn */
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for (i = 0; i < 4; i++) {
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u8 val = uli_pirq_to_irq[i*2] | (uli_pirq_to_irq[i*2+1] << 4);
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pci_write_config_byte(dev, 0x48 + i, val);
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}
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/* USB 1.1 OHCI controller 1: dev 28, func 0 - IRQ12 */
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pci_write_config_byte(dev, 0x86, ULI_PIRQD);
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/* USB 1.1 OHCI controller 2: dev 28, func 1 - IRQ9 */
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pci_write_config_byte(dev, 0x87, ULI_PIRQA);
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/* USB 1.1 OHCI controller 3: dev 28, func 2 - IRQ10 */
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pci_write_config_byte(dev, 0x88, ULI_PIRQB);
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/* Lan controller: dev 27, func 0 - IRQ6 */
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pci_write_config_byte(dev, 0x89, ULI_PIRQF);
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/* AC97 Audio controller: dev 29, func 0 - IRQ6 */
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pci_write_config_byte(dev, 0x8a, ULI_PIRQF);
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/* Modem controller: dev 29, func 1 - IRQ6 */
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pci_write_config_byte(dev, 0x8b, ULI_PIRQF);
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/* HD Audio controller: dev 29, func 2 - IRQ6 */
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pci_write_config_byte(dev, 0x8c, ULI_PIRQF);
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/* SATA controller: dev 31, func 1 - IRQ5 */
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pci_write_config_byte(dev, 0x8d, ULI_PIRQE);
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/* SMB interrupt: dev 30, func 1 - IRQ7 */
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pci_write_config_byte(dev, 0x8e, ULI_PIRQG);
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/* PMU ACPI SCI interrupt: dev 30, func 2 - IRQ7 */
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pci_write_config_byte(dev, 0x8f, ULI_PIRQG);
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/* USB 2.0 controller: dev 28, func 3 */
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pci_write_config_byte(dev, 0x74, ULI_8259_IRQ11);
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/* Primary PATA IDE IRQ: 14
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* Secondary PATA IDE IRQ: 15
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*/
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pci_write_config_byte(dev, 0x44, 0x30 | ULI_8259_IRQ14);
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pci_write_config_byte(dev, 0x75, ULI_8259_IRQ15);
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}
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static void quirk_final_uli1575(struct pci_dev *dev)
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{
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/* Set i8259 interrupt trigger
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* IRQ 3: Level
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* IRQ 4: Level
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* IRQ 5: Level
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* IRQ 6: Level
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* IRQ 7: Level
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* IRQ 9: Level
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* IRQ 10: Level
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* IRQ 11: Level
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* IRQ 12: Level
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* IRQ 14: Edge
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* IRQ 15: Edge
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*/
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if (!is_quirk_valid())
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return;
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outb(0xfa, 0x4d0);
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outb(0x1e, 0x4d1);
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/* setup RTC */
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CMOS_WRITE(RTC_SET, RTC_CONTROL);
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CMOS_WRITE(RTC_24H, RTC_CONTROL);
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/* ensure month, date, and week alarm fields are ignored */
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CMOS_WRITE(0, RTC_VALID);
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outb_p(0x7c, 0x72);
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outb_p(RTC_ALARM_DONT_CARE, 0x73);
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outb_p(0x7d, 0x72);
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outb_p(RTC_ALARM_DONT_CARE, 0x73);
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}
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/* SATA */
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static void quirk_uli5288(struct pci_dev *dev)
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{
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unsigned char c;
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unsigned int d;
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if (!is_quirk_valid())
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return;
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/* read/write lock */
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pci_read_config_byte(dev, 0x83, &c);
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pci_write_config_byte(dev, 0x83, c|0x80);
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pci_read_config_dword(dev, PCI_CLASS_REVISION, &d);
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d = (d & 0xff) | (PCI_CLASS_STORAGE_SATA_AHCI << 8);
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pci_write_config_dword(dev, PCI_CLASS_REVISION, d);
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/* restore lock */
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pci_write_config_byte(dev, 0x83, c);
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/* disable emulated PATA mode enabled */
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pci_read_config_byte(dev, 0x84, &c);
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pci_write_config_byte(dev, 0x84, c & ~0x01);
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}
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/* PATA */
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static void quirk_uli5229(struct pci_dev *dev)
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{
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unsigned short temp;
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if (!is_quirk_valid())
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return;
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pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE |
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PCI_COMMAND_MASTER | PCI_COMMAND_IO);
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/* Enable Native IRQ 14/15 */
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pci_read_config_word(dev, 0x4a, &temp);
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pci_write_config_word(dev, 0x4a, temp | 0x1000);
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}
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/* We have to do a dummy read on the P2P for the RTC to work, WTF */
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static void quirk_final_uli5249(struct pci_dev *dev)
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{
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int i;
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u8 *dummy;
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struct pci_bus *bus = dev->bus;
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struct resource *res;
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resource_size_t end = 0;
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for (i = PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCES+3; i++) {
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unsigned long flags = pci_resource_flags(dev, i);
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if ((flags & (IORESOURCE_MEM|IORESOURCE_PREFETCH)) == IORESOURCE_MEM)
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end = pci_resource_end(dev, i);
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}
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pci_bus_for_each_resource(bus, res, i) {
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if (res && res->flags & IORESOURCE_MEM) {
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if (res->end == end)
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dummy = ioremap(res->start, 0x4);
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else
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dummy = ioremap(res->end - 3, 0x4);
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if (dummy) {
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in_8(dummy);
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iounmap(dummy);
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}
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break;
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}
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}
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5249, quirk_final_uli5249);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x1575, quirk_final_uli1575);
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DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
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static void hpcd_quirk_uli1575(struct pci_dev *dev)
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{
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u32 temp32;
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if (!machine_is(mpc86xx_hpcd))
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return;
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/* Disable INTx */
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pci_read_config_dword(dev, 0x48, &temp32);
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pci_write_config_dword(dev, 0x48, (temp32 | 1<<26));
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/* Enable sideband interrupt */
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pci_read_config_dword(dev, 0x90, &temp32);
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pci_write_config_dword(dev, 0x90, (temp32 | 1<<22));
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}
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static void hpcd_quirk_uli5288(struct pci_dev *dev)
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{
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unsigned char c;
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if (!machine_is(mpc86xx_hpcd))
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return;
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pci_read_config_byte(dev, 0x83, &c);
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c |= 0x80;
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pci_write_config_byte(dev, 0x83, c);
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pci_write_config_byte(dev, PCI_CLASS_PROG, 0x01);
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pci_write_config_byte(dev, PCI_CLASS_DEVICE, 0x06);
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pci_read_config_byte(dev, 0x83, &c);
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c &= 0x7f;
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pci_write_config_byte(dev, 0x83, c);
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}
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/*
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* Since 8259PIC was disabled on the board, the IDE device can not
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* use the legacy IRQ, we need to let the IDE device work under
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* native mode and use the interrupt line like other PCI devices.
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* IRQ14 is a sideband interrupt from IDE device to CPU and we use this
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* as the interrupt for IDE device.
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*/
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static void hpcd_quirk_uli5229(struct pci_dev *dev)
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{
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unsigned char c;
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if (!machine_is(mpc86xx_hpcd))
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return;
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pci_read_config_byte(dev, 0x4b, &c);
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c |= 0x10;
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pci_write_config_byte(dev, 0x4b, c);
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}
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/*
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* SATA interrupt pin bug fix
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* There's a chip bug for 5288, The interrupt pin should be 2,
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* not the read only value 1, So it use INTB#, not INTA# which
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* actually used by the IDE device 5229.
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* As of this bug, during the PCI initialization, 5288 read the
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* irq of IDE device from the device tree, this function fix this
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* bug by re-assigning a correct irq to 5288.
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*
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*/
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static void hpcd_final_uli5288(struct pci_dev *dev)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct device_node *hosenode = hose ? hose->dn : NULL;
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struct of_irq oirq;
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int virq, pin = 2;
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u32 laddr[3];
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if (!machine_is(mpc86xx_hpcd))
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return;
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if (!hosenode)
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return;
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laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(31, 0) << 8);
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laddr[1] = laddr[2] = 0;
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of_irq_map_raw(hosenode, &pin, 1, laddr, &oirq);
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virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
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oirq.size);
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dev->irq = virq;
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, hpcd_quirk_uli1575);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, hpcd_quirk_uli5288);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, hpcd_quirk_uli5229);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5288, hpcd_final_uli5288);
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int uli_exclude_device(struct pci_controller *hose,
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u_char bus, u_char devfn)
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{
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if (bus == (hose->first_busno + 2)) {
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/* exclude Modem controller */
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if ((PCI_SLOT(devfn) == 29) && (PCI_FUNC(devfn) == 1))
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return PCIBIOS_DEVICE_NOT_FOUND;
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/* exclude HD Audio controller */
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if ((PCI_SLOT(devfn) == 29) && (PCI_FUNC(devfn) == 2))
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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