159 lines
3.8 KiB
C
159 lines
3.8 KiB
C
/*
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* intel_soc_pmic_crc.c - Device access for Crystal Cove PMIC
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*
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* Copyright (C) 2013, 2014 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version
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* 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Author: Yang, Bin <bin.yang@intel.com>
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* Author: Zhu, Lejun <lejun.zhu@linux.intel.com>
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*/
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#include <linux/mfd/core.h>
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#include <linux/interrupt.h>
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#include <linux/regmap.h>
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#include <linux/mfd/intel_soc_pmic.h>
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#include "intel_soc_pmic_core.h"
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#define CRYSTAL_COVE_MAX_REGISTER 0xC6
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#define CRYSTAL_COVE_REG_IRQLVL1 0x02
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#define CRYSTAL_COVE_REG_MIRQLVL1 0x0E
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#define CRYSTAL_COVE_IRQ_PWRSRC 0
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#define CRYSTAL_COVE_IRQ_THRM 1
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#define CRYSTAL_COVE_IRQ_BCU 2
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#define CRYSTAL_COVE_IRQ_ADC 3
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#define CRYSTAL_COVE_IRQ_CHGR 4
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#define CRYSTAL_COVE_IRQ_GPIO 5
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#define CRYSTAL_COVE_IRQ_VHDMIOCP 6
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static struct resource gpio_resources[] = {
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{
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.name = "GPIO",
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.start = CRYSTAL_COVE_IRQ_GPIO,
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.end = CRYSTAL_COVE_IRQ_GPIO,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource pwrsrc_resources[] = {
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{
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.name = "PWRSRC",
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.start = CRYSTAL_COVE_IRQ_PWRSRC,
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.end = CRYSTAL_COVE_IRQ_PWRSRC,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource adc_resources[] = {
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{
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.name = "ADC",
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.start = CRYSTAL_COVE_IRQ_ADC,
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.end = CRYSTAL_COVE_IRQ_ADC,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource thermal_resources[] = {
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{
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.name = "THERMAL",
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.start = CRYSTAL_COVE_IRQ_THRM,
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.end = CRYSTAL_COVE_IRQ_THRM,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource bcu_resources[] = {
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{
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.name = "BCU",
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.start = CRYSTAL_COVE_IRQ_BCU,
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.end = CRYSTAL_COVE_IRQ_BCU,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct mfd_cell crystal_cove_dev[] = {
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{
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.name = "crystal_cove_pwrsrc",
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.num_resources = ARRAY_SIZE(pwrsrc_resources),
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.resources = pwrsrc_resources,
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},
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{
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.name = "crystal_cove_adc",
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.num_resources = ARRAY_SIZE(adc_resources),
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.resources = adc_resources,
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},
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{
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.name = "crystal_cove_thermal",
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.num_resources = ARRAY_SIZE(thermal_resources),
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.resources = thermal_resources,
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},
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{
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.name = "crystal_cove_bcu",
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.num_resources = ARRAY_SIZE(bcu_resources),
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.resources = bcu_resources,
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},
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{
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.name = "crystal_cove_gpio",
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.num_resources = ARRAY_SIZE(gpio_resources),
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.resources = gpio_resources,
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},
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};
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static struct regmap_config crystal_cove_regmap_config = {
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.reg_bits = 8,
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.val_bits = 8,
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.max_register = CRYSTAL_COVE_MAX_REGISTER,
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.cache_type = REGCACHE_NONE,
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};
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static const struct regmap_irq crystal_cove_irqs[] = {
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[CRYSTAL_COVE_IRQ_PWRSRC] = {
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.mask = BIT(CRYSTAL_COVE_IRQ_PWRSRC),
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},
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[CRYSTAL_COVE_IRQ_THRM] = {
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.mask = BIT(CRYSTAL_COVE_IRQ_THRM),
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},
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[CRYSTAL_COVE_IRQ_BCU] = {
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.mask = BIT(CRYSTAL_COVE_IRQ_BCU),
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},
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[CRYSTAL_COVE_IRQ_ADC] = {
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.mask = BIT(CRYSTAL_COVE_IRQ_ADC),
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},
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[CRYSTAL_COVE_IRQ_CHGR] = {
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.mask = BIT(CRYSTAL_COVE_IRQ_CHGR),
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},
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[CRYSTAL_COVE_IRQ_GPIO] = {
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.mask = BIT(CRYSTAL_COVE_IRQ_GPIO),
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},
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[CRYSTAL_COVE_IRQ_VHDMIOCP] = {
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.mask = BIT(CRYSTAL_COVE_IRQ_VHDMIOCP),
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},
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};
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static struct regmap_irq_chip crystal_cove_irq_chip = {
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.name = "Crystal Cove",
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.irqs = crystal_cove_irqs,
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.num_irqs = ARRAY_SIZE(crystal_cove_irqs),
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.num_regs = 1,
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.status_base = CRYSTAL_COVE_REG_IRQLVL1,
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.mask_base = CRYSTAL_COVE_REG_MIRQLVL1,
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};
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struct intel_soc_pmic_config intel_soc_pmic_config_crc = {
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.irq_flags = IRQF_TRIGGER_RISING,
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.cell_dev = crystal_cove_dev,
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.n_cell_devs = ARRAY_SIZE(crystal_cove_dev),
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.regmap_config = &crystal_cove_regmap_config,
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.irq_chip = &crystal_cove_irq_chip,
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};
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