865 lines
22 KiB
ArmAsm
865 lines
22 KiB
ArmAsm
/*
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* This file contains idle entry/exit functions for POWER7,
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* POWER8 and POWER9 CPUs.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/threads.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/cputable.h>
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#include <asm/thread_info.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/ppc-opcode.h>
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#include <asm/hw_irq.h>
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#include <asm/kvm_book3s_asm.h>
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#include <asm/opal.h>
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#include <asm/cpuidle.h>
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#include <asm/exception-64s.h>
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#include <asm/book3s/64/mmu-hash.h>
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#include <asm/mmu.h>
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#undef DEBUG
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/*
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* Use unused space in the interrupt stack to save and restore
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* registers for winkle support.
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*/
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#define _MMCR0 GPR0
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#define _SDR1 GPR3
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#define _PTCR GPR3
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#define _RPR GPR4
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#define _SPURR GPR5
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#define _PURR GPR6
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#define _TSCR GPR7
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#define _DSCR GPR8
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#define _AMOR GPR9
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#define _WORT GPR10
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#define _WORC GPR11
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#define _LPCR GPR12
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#define PSSCR_EC_ESL_MASK_SHIFTED (PSSCR_EC | PSSCR_ESL) >> 16
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.text
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/*
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* Used by threads before entering deep idle states. Saves SPRs
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* in interrupt stack frame
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*/
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save_sprs_to_stack:
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/*
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* Note all register i.e per-core, per-subcore or per-thread is saved
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* here since any thread in the core might wake up first
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*/
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BEGIN_FTR_SECTION
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/*
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* Note - SDR1 is dropped in Power ISA v3. Hence not restoring
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* SDR1 here
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*/
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mfspr r3,SPRN_PTCR
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std r3,_PTCR(r1)
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mfspr r3,SPRN_LPCR
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std r3,_LPCR(r1)
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FTR_SECTION_ELSE
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mfspr r3,SPRN_SDR1
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std r3,_SDR1(r1)
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ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
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mfspr r3,SPRN_RPR
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std r3,_RPR(r1)
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mfspr r3,SPRN_SPURR
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std r3,_SPURR(r1)
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mfspr r3,SPRN_PURR
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std r3,_PURR(r1)
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mfspr r3,SPRN_TSCR
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std r3,_TSCR(r1)
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mfspr r3,SPRN_DSCR
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std r3,_DSCR(r1)
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mfspr r3,SPRN_AMOR
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std r3,_AMOR(r1)
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mfspr r3,SPRN_WORT
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std r3,_WORT(r1)
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mfspr r3,SPRN_WORC
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std r3,_WORC(r1)
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blr
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/*
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* Used by threads when the lock bit of core_idle_state is set.
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* Threads will spin in HMT_LOW until the lock bit is cleared.
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* r14 - pointer to core_idle_state
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* r15 - used to load contents of core_idle_state
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* r9 - used as a temporary variable
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*/
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core_idle_lock_held:
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HMT_LOW
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3: lwz r15,0(r14)
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andis. r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
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bne 3b
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HMT_MEDIUM
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lwarx r15,0,r14
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andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
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bne- core_idle_lock_held
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blr
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/*
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* Pass requested state in r3:
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* r3 - PNV_THREAD_NAP/SLEEP/WINKLE in POWER8
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* - Requested PSSCR value in POWER9
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*
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* Address of idle handler to branch to in realmode in r4
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*/
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pnv_powersave_common:
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/* Use r3 to pass state nap/sleep/winkle */
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/* NAP is a state loss, we create a regs frame on the
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* stack, fill it up with the state we care about and
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* stick a pointer to it in PACAR1. We really only
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* need to save PC, some CR bits and the NV GPRs,
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* but for now an interrupt frame will do.
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*/
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mtctr r4
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mflr r0
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std r0,16(r1)
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stdu r1,-INT_FRAME_SIZE(r1)
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std r0,_LINK(r1)
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std r0,_NIP(r1)
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/* We haven't lost state ... yet */
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li r0,0
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stb r0,PACA_NAPSTATELOST(r13)
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/* Continue saving state */
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SAVE_GPR(2, r1)
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SAVE_NVGPRS(r1)
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mfcr r5
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std r5,_CCR(r1)
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std r1,PACAR1(r13)
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/*
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* Go to real mode to do the nap, as required by the architecture.
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* Also, we need to be in real mode before setting hwthread_state,
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* because as soon as we do that, another thread can switch
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* the MMU context to the guest.
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*/
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LOAD_REG_IMMEDIATE(r7, MSR_IDLE)
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mtmsrd r7,0
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bctr
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.globl pnv_enter_arch207_idle_mode
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pnv_enter_arch207_idle_mode:
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#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
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/* Tell KVM we're entering idle */
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li r4,KVM_HWTHREAD_IN_IDLE
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/******************************************************/
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/* N O T E W E L L ! ! ! N O T E W E L L */
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/* The following store to HSTATE_HWTHREAD_STATE(r13) */
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/* MUST occur in real mode, i.e. with the MMU off, */
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/* and the MMU must stay off until we clear this flag */
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/* and test HSTATE_HWTHREAD_REQ(r13) in */
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/* pnv_powersave_wakeup in this file. */
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/* The reason is that another thread can switch the */
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/* MMU to a guest context whenever this flag is set */
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/* to KVM_HWTHREAD_IN_IDLE, and if the MMU was on, */
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/* that would potentially cause this thread to start */
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/* executing instructions from guest memory in */
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/* hypervisor mode, leading to a host crash or data */
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/* corruption, or worse. */
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/******************************************************/
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stb r4,HSTATE_HWTHREAD_STATE(r13)
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#endif
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stb r3,PACA_THREAD_IDLE_STATE(r13)
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cmpwi cr3,r3,PNV_THREAD_SLEEP
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bge cr3,2f
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IDLE_STATE_ENTER_SEQ_NORET(PPC_NAP)
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/* No return */
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2:
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/* Sleep or winkle */
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lbz r7,PACA_THREAD_MASK(r13)
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ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
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li r5,0
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beq cr3,3f
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lis r5,PNV_CORE_IDLE_WINKLE_COUNT@h
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3:
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lwarx_loop1:
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lwarx r15,0,r14
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andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
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bnel- core_idle_lock_held
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add r15,r15,r5 /* Add if winkle */
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andc r15,r15,r7 /* Clear thread bit */
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andi. r9,r15,PNV_CORE_IDLE_THREAD_BITS
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/*
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* If cr0 = 0, then current thread is the last thread of the core entering
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* sleep. Last thread needs to execute the hardware bug workaround code if
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* required by the platform.
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* Make the workaround call unconditionally here. The below branch call is
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* patched out when the idle states are discovered if the platform does not
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* require it.
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*/
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.global pnv_fastsleep_workaround_at_entry
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pnv_fastsleep_workaround_at_entry:
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beq fastsleep_workaround_at_entry
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stwcx. r15,0,r14
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bne- lwarx_loop1
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isync
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common_enter: /* common code for all the threads entering sleep or winkle */
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bgt cr3,enter_winkle
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IDLE_STATE_ENTER_SEQ_NORET(PPC_SLEEP)
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fastsleep_workaround_at_entry:
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oris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
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stwcx. r15,0,r14
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bne- lwarx_loop1
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isync
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/* Fast sleep workaround */
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li r3,1
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li r4,1
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bl opal_config_cpu_idle_state
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/* Unlock */
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xoris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
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lwsync
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stw r15,0(r14)
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b common_enter
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enter_winkle:
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bl save_sprs_to_stack
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IDLE_STATE_ENTER_SEQ_NORET(PPC_WINKLE)
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/*
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* r3 - PSSCR value corresponding to the requested stop state.
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*/
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power_enter_stop:
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#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
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/* Tell KVM we're entering idle */
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li r4,KVM_HWTHREAD_IN_IDLE
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/* DO THIS IN REAL MODE! See comment above. */
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stb r4,HSTATE_HWTHREAD_STATE(r13)
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#endif
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/*
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* Check if we are executing the lite variant with ESL=EC=0
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*/
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andis. r4,r3,PSSCR_EC_ESL_MASK_SHIFTED
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clrldi r3,r3,60 /* r3 = Bits[60:63] = Requested Level (RL) */
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bne .Lhandle_esl_ec_set
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IDLE_STATE_ENTER_SEQ(PPC_STOP)
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li r3,0 /* Since we didn't lose state, return 0 */
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/*
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* pnv_wakeup_noloss() expects r12 to contain the SRR1 value so
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* it can determine if the wakeup reason is an HMI in
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* CHECK_HMI_INTERRUPT.
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*
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* However, when we wakeup with ESL=0, SRR1 will not contain the wakeup
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* reason, so there is no point setting r12 to SRR1.
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*
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* Further, we clear r12 here, so that we don't accidentally enter the
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* HMI in pnv_wakeup_noloss() if the value of r12[42:45] == WAKE_HMI.
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*/
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li r12, 0
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b pnv_wakeup_noloss
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.Lhandle_esl_ec_set:
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/*
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* POWER9 DD2 can incorrectly set PMAO when waking up after a
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* state-loss idle. Saving and restoring MMCR0 over idle is a
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* workaround.
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*/
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mfspr r4,SPRN_MMCR0
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std r4,_MMCR0(r1)
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/*
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* Check if the requested state is a deep idle state.
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*/
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LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
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ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
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cmpd r3,r4
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bge .Lhandle_deep_stop
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IDLE_STATE_ENTER_SEQ_NORET(PPC_STOP)
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.Lhandle_deep_stop:
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/*
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* Entering deep idle state.
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* Clear thread bit in PACA_CORE_IDLE_STATE, save SPRs to
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* stack and enter stop
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*/
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lbz r7,PACA_THREAD_MASK(r13)
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ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
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lwarx_loop_stop:
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lwarx r15,0,r14
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andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
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bnel- core_idle_lock_held
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andc r15,r15,r7 /* Clear thread bit */
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stwcx. r15,0,r14
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bne- lwarx_loop_stop
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isync
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bl save_sprs_to_stack
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IDLE_STATE_ENTER_SEQ_NORET(PPC_STOP)
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/*
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* Entered with MSR[EE]=0 and no soft-masked interrupts pending.
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* r3 contains desired idle state (PNV_THREAD_NAP/SLEEP/WINKLE).
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*/
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_GLOBAL(power7_idle_insn)
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/* Now check if user or arch enabled NAP mode */
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LOAD_REG_ADDR(r4, pnv_enter_arch207_idle_mode)
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b pnv_powersave_common
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#define CHECK_HMI_INTERRUPT \
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BEGIN_FTR_SECTION_NESTED(66); \
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rlwinm r0,r12,45-31,0xf; /* extract wake reason field (P8) */ \
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FTR_SECTION_ELSE_NESTED(66); \
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rlwinm r0,r12,45-31,0xe; /* P7 wake reason field is 3 bits */ \
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ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \
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cmpwi r0,0xa; /* Hypervisor maintenance ? */ \
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bne+ 20f; \
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/* Invoke opal call to handle hmi */ \
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ld r2,PACATOC(r13); \
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ld r1,PACAR1(r13); \
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std r3,ORIG_GPR3(r1); /* Save original r3 */ \
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li r3,0; /* NULL argument */ \
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bl hmi_exception_realmode; \
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nop; \
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ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \
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20: nop;
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/*
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* Entered with MSR[EE]=0 and no soft-masked interrupts pending.
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* r3 contains desired PSSCR register value.
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*/
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_GLOBAL(power9_idle_stop)
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std r3, PACA_REQ_PSSCR(r13)
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mtspr SPRN_PSSCR,r3
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LOAD_REG_ADDR(r4,power_enter_stop)
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b pnv_powersave_common
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/* No return */
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/*
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* On waking up from stop 0,1,2 with ESL=1 on POWER9 DD1,
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* HSPRG0 will be set to the HSPRG0 value of one of the
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* threads in this core. Thus the value we have in r13
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* may not be this thread's paca pointer.
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*
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* Fortunately, the TIR remains invariant. Since this thread's
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* paca pointer is recorded in all its sibling's paca, we can
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* correctly recover this thread's paca pointer if we
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* know the index of this thread in the core.
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*
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* This index can be obtained from the TIR.
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*
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* i.e, thread's position in the core = TIR.
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* If this value is i, then this thread's paca is
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* paca->thread_sibling_pacas[i].
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*/
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power9_dd1_recover_paca:
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mfspr r4, SPRN_TIR
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/*
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* Since each entry in thread_sibling_pacas is 8 bytes
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* we need to left-shift by 3 bits. Thus r4 = i * 8
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*/
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sldi r4, r4, 3
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/* Get &paca->thread_sibling_pacas[0] in r5 */
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ld r5, PACA_SIBLING_PACA_PTRS(r13)
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/* Load paca->thread_sibling_pacas[i] into r13 */
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ldx r13, r4, r5
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SET_PACA(r13)
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/*
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* Indicate that we have lost NVGPR state
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* which needs to be restored from the stack.
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*/
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li r3, 1
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stb r3,PACA_NAPSTATELOST(r13)
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blr
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/*
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* Called from machine check handler for powersave wakeups.
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* Low level machine check processing has already been done. Now just
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* go through the wake up path to get everything in order.
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*
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* r3 - The original SRR1 value.
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* Original SRR[01] have been clobbered.
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* MSR_RI is clear.
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*/
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.global pnv_powersave_wakeup_mce
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pnv_powersave_wakeup_mce:
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/* Set cr3 for pnv_powersave_wakeup */
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rlwinm r11,r3,47-31,30,31
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cmpwi cr3,r11,2
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/*
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* Now put the original SRR1 with SRR1_WAKEMCE_RESVD as the wake
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* reason into r12, which allows reuse of the system reset wakeup
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* code without being mistaken for another type of wakeup.
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*/
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oris r12,r3,SRR1_WAKEMCE_RESVD@h
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b pnv_powersave_wakeup
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/*
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* Called from reset vector for powersave wakeups.
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* cr3 - set to gt if waking up with partial/complete hypervisor state loss
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* r12 - SRR1
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*/
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.global pnv_powersave_wakeup
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pnv_powersave_wakeup:
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ld r2, PACATOC(r13)
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|
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BEGIN_FTR_SECTION
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BEGIN_FTR_SECTION_NESTED(70)
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bl power9_dd1_recover_paca
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END_FTR_SECTION_NESTED_IFSET(CPU_FTR_POWER9_DD1, 70)
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bl pnv_restore_hyp_resource_arch300
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FTR_SECTION_ELSE
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bl pnv_restore_hyp_resource_arch207
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ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
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|
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li r0,PNV_THREAD_RUNNING
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stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */
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|
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mr r3,r12
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#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
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li r0,KVM_HWTHREAD_IN_KERNEL
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stb r0,HSTATE_HWTHREAD_STATE(r13)
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/* Order setting hwthread_state vs. testing hwthread_req */
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sync
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lbz r0,HSTATE_HWTHREAD_REQ(r13)
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cmpwi r0,0
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beq 1f
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b kvm_start_guest
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1:
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#endif
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|
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/* Return SRR1 from power7_nap() */
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blt cr3,pnv_wakeup_noloss
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b pnv_wakeup_loss
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|
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/*
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* Check whether we have woken up with hypervisor state loss.
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* If yes, restore hypervisor state and return back to link.
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*
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* cr3 - set to gt if waking up with partial/complete hypervisor state loss
|
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*/
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pnv_restore_hyp_resource_arch300:
|
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/*
|
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* Workaround for POWER9, if we lost resources, the ERAT
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* might have been mixed up and needs flushing. We also need
|
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* to reload MMCR0 (see comment above).
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*/
|
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blt cr3,1f
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PPC_INVALIDATE_ERAT
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ld r1,PACAR1(r13)
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ld r4,_MMCR0(r1)
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mtspr SPRN_MMCR0,r4
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1:
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/*
|
|
* POWER ISA 3. Use PSSCR to determine if we
|
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* are waking up from deep idle state
|
|
*/
|
|
LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
|
|
ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
|
|
|
|
BEGIN_FTR_SECTION_NESTED(71)
|
|
/*
|
|
* Assume that we are waking up from the state
|
|
* same as the Requested Level (RL) in the PSSCR
|
|
* which are Bits 60-63
|
|
*/
|
|
ld r5,PACA_REQ_PSSCR(r13)
|
|
rldicl r5,r5,0,60
|
|
FTR_SECTION_ELSE_NESTED(71)
|
|
/*
|
|
* 0-3 bits correspond to Power-Saving Level Status
|
|
* which indicates the idle state we are waking up from
|
|
*/
|
|
mfspr r5, SPRN_PSSCR
|
|
rldicl r5,r5,4,60
|
|
ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_POWER9_DD1, 71)
|
|
cmpd cr4,r5,r4
|
|
bge cr4,pnv_wakeup_tb_loss /* returns to caller */
|
|
|
|
blr /* Waking up without hypervisor state loss. */
|
|
|
|
/* Same calling convention as arch300 */
|
|
pnv_restore_hyp_resource_arch207:
|
|
/*
|
|
* POWER ISA 2.07 or less.
|
|
* Check if we slept with sleep or winkle.
|
|
*/
|
|
lbz r4,PACA_THREAD_IDLE_STATE(r13)
|
|
cmpwi cr2,r4,PNV_THREAD_NAP
|
|
bgt cr2,pnv_wakeup_tb_loss /* Either sleep or Winkle */
|
|
|
|
/*
|
|
* We fall through here if PACA_THREAD_IDLE_STATE shows we are waking
|
|
* up from nap. At this stage CR3 shouldn't contains 'gt' since that
|
|
* indicates we are waking with hypervisor state loss from nap.
|
|
*/
|
|
bgt cr3,.
|
|
|
|
blr /* Waking up without hypervisor state loss */
|
|
|
|
/*
|
|
* Called if waking up from idle state which can cause either partial or
|
|
* complete hyp state loss.
|
|
* In POWER8, called if waking up from fastsleep or winkle
|
|
* In POWER9, called if waking up from stop state >= pnv_first_deep_stop_state
|
|
*
|
|
* r13 - PACA
|
|
* cr3 - gt if waking up with partial/complete hypervisor state loss
|
|
*
|
|
* If ISA300:
|
|
* cr4 - gt or eq if waking up from complete hypervisor state loss.
|
|
*
|
|
* If ISA207:
|
|
* r4 - PACA_THREAD_IDLE_STATE
|
|
*/
|
|
pnv_wakeup_tb_loss:
|
|
ld r1,PACAR1(r13)
|
|
/*
|
|
* Before entering any idle state, the NVGPRs are saved in the stack.
|
|
* If there was a state loss, or PACA_NAPSTATELOST was set, then the
|
|
* NVGPRs are restored. If we are here, it is likely that state is lost,
|
|
* but not guaranteed -- neither ISA207 nor ISA300 tests to reach
|
|
* here are the same as the test to restore NVGPRS:
|
|
* PACA_THREAD_IDLE_STATE test for ISA207, PSSCR test for ISA300,
|
|
* and SRR1 test for restoring NVGPRs.
|
|
*
|
|
* We are about to clobber NVGPRs now, so set NAPSTATELOST to
|
|
* guarantee they will always be restored. This might be tightened
|
|
* with careful reading of specs (particularly for ISA300) but this
|
|
* is already a slow wakeup path and it's simpler to be safe.
|
|
*/
|
|
li r0,1
|
|
stb r0,PACA_NAPSTATELOST(r13)
|
|
|
|
/*
|
|
*
|
|
* Save SRR1 and LR in NVGPRs as they might be clobbered in
|
|
* opal_call() (called in CHECK_HMI_INTERRUPT). SRR1 is required
|
|
* to determine the wakeup reason if we branch to kvm_start_guest. LR
|
|
* is required to return back to reset vector after hypervisor state
|
|
* restore is complete.
|
|
*/
|
|
mr r19,r12
|
|
mr r18,r4
|
|
mflr r17
|
|
BEGIN_FTR_SECTION
|
|
CHECK_HMI_INTERRUPT
|
|
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
|
|
|
|
ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
|
|
lbz r7,PACA_THREAD_MASK(r13)
|
|
|
|
/*
|
|
* Take the core lock to synchronize against other threads.
|
|
*
|
|
* Lock bit is set in one of the 2 cases-
|
|
* a. In the sleep/winkle enter path, the last thread is executing
|
|
* fastsleep workaround code.
|
|
* b. In the wake up path, another thread is executing fastsleep
|
|
* workaround undo code or resyncing timebase or restoring context
|
|
* In either case loop until the lock bit is cleared.
|
|
*/
|
|
1:
|
|
lwarx r15,0,r14
|
|
andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
|
|
bnel- core_idle_lock_held
|
|
oris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
|
|
stwcx. r15,0,r14
|
|
bne- 1b
|
|
isync
|
|
|
|
andi. r9,r15,PNV_CORE_IDLE_THREAD_BITS
|
|
cmpwi cr2,r9,0
|
|
|
|
/*
|
|
* At this stage
|
|
* cr2 - eq if first thread to wakeup in core
|
|
* cr3- gt if waking up with partial/complete hypervisor state loss
|
|
* ISA300:
|
|
* cr4 - gt or eq if waking up from complete hypervisor state loss.
|
|
*/
|
|
|
|
BEGIN_FTR_SECTION
|
|
/*
|
|
* Were we in winkle?
|
|
* If yes, check if all threads were in winkle, decrement our
|
|
* winkle count, set all thread winkle bits if all were in winkle.
|
|
* Check if our thread has a winkle bit set, and set cr4 accordingly
|
|
* (to match ISA300, above). Pseudo-code for core idle state
|
|
* transitions for ISA207 is as follows (everything happens atomically
|
|
* due to store conditional and/or lock bit):
|
|
*
|
|
* nap_idle() { }
|
|
* nap_wake() { }
|
|
*
|
|
* sleep_idle()
|
|
* {
|
|
* core_idle_state &= ~thread_in_core
|
|
* }
|
|
*
|
|
* sleep_wake()
|
|
* {
|
|
* bool first_in_core, first_in_subcore;
|
|
*
|
|
* first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0;
|
|
* first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0;
|
|
*
|
|
* core_idle_state |= thread_in_core;
|
|
* }
|
|
*
|
|
* winkle_idle()
|
|
* {
|
|
* core_idle_state &= ~thread_in_core;
|
|
* core_idle_state += 1 << WINKLE_COUNT_SHIFT;
|
|
* }
|
|
*
|
|
* winkle_wake()
|
|
* {
|
|
* bool first_in_core, first_in_subcore, winkle_state_lost;
|
|
*
|
|
* first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0;
|
|
* first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0;
|
|
*
|
|
* core_idle_state |= thread_in_core;
|
|
*
|
|
* if ((core_idle_state & WINKLE_MASK) == (8 << WINKLE_COUNT_SIHFT))
|
|
* core_idle_state |= THREAD_WINKLE_BITS;
|
|
* core_idle_state -= 1 << WINKLE_COUNT_SHIFT;
|
|
*
|
|
* winkle_state_lost = core_idle_state &
|
|
* (thread_in_core << WINKLE_THREAD_SHIFT);
|
|
* core_idle_state &= ~(thread_in_core << WINKLE_THREAD_SHIFT);
|
|
* }
|
|
*
|
|
*/
|
|
cmpwi r18,PNV_THREAD_WINKLE
|
|
bne 2f
|
|
andis. r9,r15,PNV_CORE_IDLE_WINKLE_COUNT_ALL_BIT@h
|
|
subis r15,r15,PNV_CORE_IDLE_WINKLE_COUNT@h
|
|
beq 2f
|
|
ori r15,r15,PNV_CORE_IDLE_THREAD_WINKLE_BITS /* all were winkle */
|
|
2:
|
|
/* Shift thread bit to winkle mask, then test if this thread is set,
|
|
* and remove it from the winkle bits */
|
|
slwi r8,r7,8
|
|
and r8,r8,r15
|
|
andc r15,r15,r8
|
|
cmpwi cr4,r8,1 /* cr4 will be gt if our bit is set, lt if not */
|
|
|
|
lbz r4,PACA_SUBCORE_SIBLING_MASK(r13)
|
|
and r4,r4,r15
|
|
cmpwi r4,0 /* Check if first in subcore */
|
|
|
|
or r15,r15,r7 /* Set thread bit */
|
|
beq first_thread_in_subcore
|
|
END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
|
|
|
|
or r15,r15,r7 /* Set thread bit */
|
|
beq cr2,first_thread_in_core
|
|
|
|
/* Not first thread in core or subcore to wake up */
|
|
b clear_lock
|
|
|
|
first_thread_in_subcore:
|
|
/*
|
|
* If waking up from sleep, subcore state is not lost. Hence
|
|
* skip subcore state restore
|
|
*/
|
|
blt cr4,subcore_state_restored
|
|
|
|
/* Restore per-subcore state */
|
|
ld r4,_SDR1(r1)
|
|
mtspr SPRN_SDR1,r4
|
|
|
|
ld r4,_RPR(r1)
|
|
mtspr SPRN_RPR,r4
|
|
ld r4,_AMOR(r1)
|
|
mtspr SPRN_AMOR,r4
|
|
|
|
subcore_state_restored:
|
|
/*
|
|
* Check if the thread is also the first thread in the core. If not,
|
|
* skip to clear_lock.
|
|
*/
|
|
bne cr2,clear_lock
|
|
|
|
first_thread_in_core:
|
|
|
|
/*
|
|
* First thread in the core waking up from any state which can cause
|
|
* partial or complete hypervisor state loss. It needs to
|
|
* call the fastsleep workaround code if the platform requires it.
|
|
* Call it unconditionally here. The below branch instruction will
|
|
* be patched out if the platform does not have fastsleep or does not
|
|
* require the workaround. Patching will be performed during the
|
|
* discovery of idle-states.
|
|
*/
|
|
.global pnv_fastsleep_workaround_at_exit
|
|
pnv_fastsleep_workaround_at_exit:
|
|
b fastsleep_workaround_at_exit
|
|
|
|
timebase_resync:
|
|
/*
|
|
* Use cr3 which indicates that we are waking up with atleast partial
|
|
* hypervisor state loss to determine if TIMEBASE RESYNC is needed.
|
|
*/
|
|
ble cr3,.Ltb_resynced
|
|
/* Time base re-sync */
|
|
bl opal_resync_timebase;
|
|
/*
|
|
* If waking up from sleep (POWER8), per core state
|
|
* is not lost, skip to clear_lock.
|
|
*/
|
|
.Ltb_resynced:
|
|
blt cr4,clear_lock
|
|
|
|
/*
|
|
* First thread in the core to wake up and its waking up with
|
|
* complete hypervisor state loss. Restore per core hypervisor
|
|
* state.
|
|
*/
|
|
BEGIN_FTR_SECTION
|
|
ld r4,_PTCR(r1)
|
|
mtspr SPRN_PTCR,r4
|
|
ld r4,_RPR(r1)
|
|
mtspr SPRN_RPR,r4
|
|
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
|
|
|
|
ld r4,_TSCR(r1)
|
|
mtspr SPRN_TSCR,r4
|
|
ld r4,_WORC(r1)
|
|
mtspr SPRN_WORC,r4
|
|
|
|
clear_lock:
|
|
xoris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
|
|
lwsync
|
|
stw r15,0(r14)
|
|
|
|
common_exit:
|
|
/*
|
|
* Common to all threads.
|
|
*
|
|
* If waking up from sleep, hypervisor state is not lost. Hence
|
|
* skip hypervisor state restore.
|
|
*/
|
|
blt cr4,hypervisor_state_restored
|
|
|
|
/* Waking up from winkle */
|
|
|
|
BEGIN_MMU_FTR_SECTION
|
|
b no_segments
|
|
END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
|
|
/* Restore SLB from PACA */
|
|
ld r8,PACA_SLBSHADOWPTR(r13)
|
|
|
|
.rept SLB_NUM_BOLTED
|
|
li r3, SLBSHADOW_SAVEAREA
|
|
LDX_BE r5, r8, r3
|
|
addi r3, r3, 8
|
|
LDX_BE r6, r8, r3
|
|
andis. r7,r5,SLB_ESID_V@h
|
|
beq 1f
|
|
slbmte r6,r5
|
|
1: addi r8,r8,16
|
|
.endr
|
|
no_segments:
|
|
|
|
/* Restore per thread state */
|
|
|
|
ld r4,_SPURR(r1)
|
|
mtspr SPRN_SPURR,r4
|
|
ld r4,_PURR(r1)
|
|
mtspr SPRN_PURR,r4
|
|
ld r4,_DSCR(r1)
|
|
mtspr SPRN_DSCR,r4
|
|
ld r4,_WORT(r1)
|
|
mtspr SPRN_WORT,r4
|
|
|
|
/* Call cur_cpu_spec->cpu_restore() */
|
|
LOAD_REG_ADDR(r4, cur_cpu_spec)
|
|
ld r4,0(r4)
|
|
ld r12,CPU_SPEC_RESTORE(r4)
|
|
#ifdef PPC64_ELF_ABI_v1
|
|
ld r12,0(r12)
|
|
#endif
|
|
mtctr r12
|
|
bctrl
|
|
|
|
BEGIN_FTR_SECTION
|
|
ld r4,_LPCR(r1)
|
|
mtspr SPRN_LPCR,r4
|
|
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
|
|
hypervisor_state_restored:
|
|
|
|
mr r12,r19
|
|
mtlr r17
|
|
blr /* return to pnv_powersave_wakeup */
|
|
|
|
fastsleep_workaround_at_exit:
|
|
li r3,1
|
|
li r4,0
|
|
bl opal_config_cpu_idle_state
|
|
b timebase_resync
|
|
|
|
/*
|
|
* R3 here contains the value that will be returned to the caller
|
|
* of power7_nap.
|
|
* R12 contains SRR1 for CHECK_HMI_INTERRUPT.
|
|
*/
|
|
.global pnv_wakeup_loss
|
|
pnv_wakeup_loss:
|
|
ld r1,PACAR1(r13)
|
|
BEGIN_FTR_SECTION
|
|
CHECK_HMI_INTERRUPT
|
|
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
|
|
REST_NVGPRS(r1)
|
|
REST_GPR(2, r1)
|
|
ld r4,PACAKMSR(r13)
|
|
ld r5,_LINK(r1)
|
|
ld r6,_CCR(r1)
|
|
addi r1,r1,INT_FRAME_SIZE
|
|
mtlr r5
|
|
mtcr r6
|
|
mtmsrd r4
|
|
blr
|
|
|
|
/*
|
|
* R3 here contains the value that will be returned to the caller
|
|
* of power7_nap.
|
|
* R12 contains SRR1 for CHECK_HMI_INTERRUPT.
|
|
*/
|
|
pnv_wakeup_noloss:
|
|
lbz r0,PACA_NAPSTATELOST(r13)
|
|
cmpwi r0,0
|
|
bne pnv_wakeup_loss
|
|
ld r1,PACAR1(r13)
|
|
BEGIN_FTR_SECTION
|
|
CHECK_HMI_INTERRUPT
|
|
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
|
|
ld r4,PACAKMSR(r13)
|
|
ld r5,_NIP(r1)
|
|
ld r6,_CCR(r1)
|
|
addi r1,r1,INT_FRAME_SIZE
|
|
mtlr r5
|
|
mtcr r6
|
|
mtmsrd r4
|
|
blr
|