217 lines
5.4 KiB
ArmAsm
217 lines
5.4 KiB
ArmAsm
/*
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* linux/arch/arm/mm/cache-v4wb.S
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*
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* Copyright (C) 1997-2002 Russell king
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/config.h>
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/hardware.h>
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#include <asm/page.h>
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#include "proc-macros.S"
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/*
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* The size of one data cache line.
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*/
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#define CACHE_DLINESIZE 32
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/*
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* The total size of the data cache.
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*/
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#if defined(CONFIG_CPU_SA110)
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# define CACHE_DSIZE 16384
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#elif defined(CONFIG_CPU_SA1100)
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# define CACHE_DSIZE 8192
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#else
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# error Unknown cache size
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#endif
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/*
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* This is the size at which it becomes more efficient to
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* clean the whole cache, rather than using the individual
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* cache line maintainence instructions.
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*
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* Size Clean (ticks) Dirty (ticks)
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* 4096 21 20 21 53 55 54
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* 8192 40 41 40 106 100 102
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* 16384 77 77 76 140 140 138
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* 32768 150 149 150 214 216 212 <---
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* 65536 296 297 296 351 358 361
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* 131072 591 591 591 656 657 651
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* Whole 132 136 132 221 217 207 <---
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*/
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#define CACHE_DLIMIT (CACHE_DSIZE * 4)
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/*
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* flush_user_cache_all()
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*
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* Clean and invalidate all cache entries in a particular address
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* space.
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*/
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ENTRY(v4wb_flush_user_cache_all)
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/* FALLTHROUGH */
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/*
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* flush_kern_cache_all()
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*
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* Clean and invalidate the entire cache.
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*/
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ENTRY(v4wb_flush_kern_cache_all)
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mov ip, #0
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mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
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__flush_whole_cache:
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mov r0, #FLUSH_BASE
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add r1, r0, #CACHE_DSIZE
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1: ldr r2, [r0], #32
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cmp r0, r1
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blo 1b
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mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
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mov pc, lr
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/*
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* flush_user_cache_range(start, end, flags)
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*
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* Invalidate a range of cache entries in the specified
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* address space.
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*
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* - start - start address (inclusive, page aligned)
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* - end - end address (exclusive, page aligned)
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* - flags - vma_area_struct flags describing address space
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*/
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ENTRY(v4wb_flush_user_cache_range)
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sub r3, r1, r0 @ calculate total size
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tst r2, #VM_EXEC @ executable region?
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mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
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cmp r3, #CACHE_DLIMIT @ total size >= limit?
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bhs __flush_whole_cache @ flush whole D cache
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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tst r2, #VM_EXEC
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mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer
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mov pc, lr
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/*
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* flush_kern_dcache_page(void *page)
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*
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* Ensure no D cache aliasing occurs, either with itself or
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* the I cache
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*
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* - addr - page aligned address
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*/
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ENTRY(v4wb_flush_kern_dcache_page)
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add r1, r0, #PAGE_SZ
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/* fall through */
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/*
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* coherent_kern_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(v4wb_coherent_kern_range)
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/* fall through */
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/*
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* coherent_user_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(v4wb_coherent_user_range)
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mov ip, #0
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mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* dma_inv_range(start, end)
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*
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* Invalidate (discard) the specified virtual address range.
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* May not write back any entries. If 'start' or 'end'
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* are not cache line aligned, those lines must be written
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* back.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(v4wb_dma_inv_range)
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tst r0, #CACHE_DLINESIZE - 1
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bic r0, r0, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
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tst r1, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
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1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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mov pc, lr
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/*
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* dma_clean_range(start, end)
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*
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* Clean (write back) the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(v4wb_dma_clean_range)
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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mov pc, lr
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/*
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* dma_flush_range(start, end)
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*
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* Clean and invalidate the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*
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* This is actually the same as v4wb_coherent_kern_range()
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*/
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.globl v4wb_dma_flush_range
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.set v4wb_dma_flush_range, v4wb_coherent_kern_range
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__INITDATA
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.type v4wb_cache_fns, #object
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ENTRY(v4wb_cache_fns)
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.long v4wb_flush_kern_cache_all
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.long v4wb_flush_user_cache_all
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.long v4wb_flush_user_cache_range
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.long v4wb_coherent_kern_range
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.long v4wb_coherent_user_range
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.long v4wb_flush_kern_dcache_page
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.long v4wb_dma_inv_range
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.long v4wb_dma_clean_range
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.long v4wb_dma_flush_range
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.size v4wb_cache_fns, . - v4wb_cache_fns
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