386 lines
9.7 KiB
C
386 lines
9.7 KiB
C
/*
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* Copyright (C) 2005 - 2009 ServerEngines
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation. The full GNU General
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* Public License is included in this distribution in the file called COPYING.
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*
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* Contact Information:
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* linux-drivers@serverengines.com
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*
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* ServerEngines
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* 209 N. Fair Oaks Ave
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* Sunnyvale, CA 94085
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*/
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#ifndef BE_H
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#define BE_H
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#include <linux/pci.h>
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#include <linux/etherdevice.h>
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#include <linux/version.h>
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#include <linux/delay.h>
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#include <net/tcp.h>
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#include <net/ip.h>
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#include <net/ipv6.h>
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#include <linux/if_vlan.h>
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#include <linux/workqueue.h>
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#include <linux/interrupt.h>
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#include <linux/firmware.h>
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#include "be_hw.h"
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#define DRV_VER "2.101.346u"
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#define DRV_NAME "be2net"
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#define BE_NAME "ServerEngines BladeEngine2 10Gbps NIC"
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#define BE3_NAME "ServerEngines BladeEngine3 10Gbps NIC"
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#define OC_NAME "Emulex OneConnect 10Gbps NIC"
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#define OC_NAME1 "Emulex OneConnect 10Gbps NIC (be3)"
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#define DRV_DESC BE_NAME "Driver"
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#define BE_VENDOR_ID 0x19a2
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#define BE_DEVICE_ID1 0x211
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#define BE_DEVICE_ID2 0x221
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#define OC_DEVICE_ID1 0x700
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#define OC_DEVICE_ID2 0x701
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#define OC_DEVICE_ID3 0x710
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static inline char *nic_name(struct pci_dev *pdev)
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{
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switch (pdev->device) {
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case OC_DEVICE_ID1:
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case OC_DEVICE_ID2:
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return OC_NAME;
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case OC_DEVICE_ID3:
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return OC_NAME1;
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case BE_DEVICE_ID2:
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return BE3_NAME;
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default:
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return BE_NAME;
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}
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}
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/* Number of bytes of an RX frame that are copied to skb->data */
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#define BE_HDR_LEN 64
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#define BE_MAX_JUMBO_FRAME_SIZE 9018
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#define BE_MIN_MTU 256
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#define BE_NUM_VLANS_SUPPORTED 64
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#define BE_MAX_EQD 96
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#define BE_MAX_TX_FRAG_COUNT 30
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#define EVNT_Q_LEN 1024
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#define TX_Q_LEN 2048
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#define TX_CQ_LEN 1024
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#define RX_Q_LEN 1024 /* Does not support any other value */
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#define RX_CQ_LEN 1024
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#define MCC_Q_LEN 128 /* total size not to exceed 8 pages */
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#define MCC_CQ_LEN 256
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#define BE_NAPI_WEIGHT 64
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#define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */
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#define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST)
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#define FW_VER_LEN 32
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struct be_dma_mem {
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void *va;
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dma_addr_t dma;
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u32 size;
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};
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struct be_queue_info {
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struct be_dma_mem dma_mem;
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u16 len;
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u16 entry_size; /* Size of an element in the queue */
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u16 id;
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u16 tail, head;
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bool created;
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atomic_t used; /* Number of valid elements in the queue */
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};
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static inline u32 MODULO(u16 val, u16 limit)
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{
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BUG_ON(limit & (limit - 1));
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return val & (limit - 1);
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}
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static inline void index_adv(u16 *index, u16 val, u16 limit)
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{
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*index = MODULO((*index + val), limit);
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}
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static inline void index_inc(u16 *index, u16 limit)
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{
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*index = MODULO((*index + 1), limit);
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}
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static inline void *queue_head_node(struct be_queue_info *q)
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{
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return q->dma_mem.va + q->head * q->entry_size;
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}
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static inline void *queue_tail_node(struct be_queue_info *q)
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{
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return q->dma_mem.va + q->tail * q->entry_size;
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}
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static inline void queue_head_inc(struct be_queue_info *q)
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{
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index_inc(&q->head, q->len);
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}
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static inline void queue_tail_inc(struct be_queue_info *q)
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{
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index_inc(&q->tail, q->len);
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}
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struct be_eq_obj {
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struct be_queue_info q;
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char desc[32];
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/* Adaptive interrupt coalescing (AIC) info */
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bool enable_aic;
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u16 min_eqd; /* in usecs */
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u16 max_eqd; /* in usecs */
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u16 cur_eqd; /* in usecs */
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struct napi_struct napi;
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};
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struct be_mcc_obj {
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struct be_queue_info q;
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struct be_queue_info cq;
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};
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struct be_drvr_stats {
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u32 be_tx_reqs; /* number of TX requests initiated */
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u32 be_tx_stops; /* number of times TX Q was stopped */
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u32 be_fwd_reqs; /* number of send reqs through forwarding i/f */
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u32 be_tx_wrbs; /* number of tx WRBs used */
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u32 be_tx_events; /* number of tx completion events */
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u32 be_tx_compl; /* number of tx completion entries processed */
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ulong be_tx_jiffies;
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u64 be_tx_bytes;
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u64 be_tx_bytes_prev;
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u32 be_tx_rate;
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u32 cache_barrier[16];
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u32 be_ethrx_post_fail;/* number of ethrx buffer alloc failures */
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u32 be_rx_polls; /* number of times NAPI called poll function */
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u32 be_rx_events; /* number of ucast rx completion events */
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u32 be_rx_compl; /* number of rx completion entries processed */
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ulong be_rx_jiffies;
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u64 be_rx_bytes;
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u64 be_rx_bytes_prev;
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u32 be_rx_rate;
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/* number of non ether type II frames dropped where
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* frame len > length field of Mac Hdr */
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u32 be_802_3_dropped_frames;
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/* number of non ether type II frames malformed where
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* in frame len < length field of Mac Hdr */
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u32 be_802_3_malformed_frames;
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u32 be_rxcp_err; /* Num rx completion entries w/ err set. */
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ulong rx_fps_jiffies; /* jiffies at last FPS calc */
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u32 be_rx_frags;
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u32 be_prev_rx_frags;
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u32 be_rx_fps; /* Rx frags per second */
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};
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struct be_stats_obj {
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struct be_drvr_stats drvr_stats;
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struct be_dma_mem cmd;
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};
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struct be_tx_obj {
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struct be_queue_info q;
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struct be_queue_info cq;
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/* Remember the skbs that were transmitted */
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struct sk_buff *sent_skb_list[TX_Q_LEN];
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};
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/* Struct to remember the pages posted for rx frags */
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struct be_rx_page_info {
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struct page *page;
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dma_addr_t bus;
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u16 page_offset;
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bool last_page_user;
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};
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struct be_rx_obj {
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struct be_queue_info q;
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struct be_queue_info cq;
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struct be_rx_page_info page_info_tbl[RX_Q_LEN];
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};
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#define BE_NUM_MSIX_VECTORS 2 /* 1 each for Tx and Rx */
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struct be_adapter {
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struct pci_dev *pdev;
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struct net_device *netdev;
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u8 __iomem *csr;
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u8 __iomem *db; /* Door Bell */
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u8 __iomem *pcicfg; /* PCI config space */
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spinlock_t mbox_lock; /* For serializing mbox cmds to BE card */
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struct be_dma_mem mbox_mem;
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/* Mbox mem is adjusted to align to 16 bytes. The allocated addr
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* is stored for freeing purpose */
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struct be_dma_mem mbox_mem_alloced;
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struct be_mcc_obj mcc_obj;
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spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */
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spinlock_t mcc_cq_lock;
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struct msix_entry msix_entries[BE_NUM_MSIX_VECTORS];
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bool msix_enabled;
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bool isr_registered;
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/* TX Rings */
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struct be_eq_obj tx_eq;
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struct be_tx_obj tx_obj;
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u32 cache_line_break[8];
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/* Rx rings */
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struct be_eq_obj rx_eq;
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struct be_rx_obj rx_obj;
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u32 big_page_size; /* Compounded page size shared by rx wrbs */
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bool rx_post_starved; /* Zero rx frags have been posted to BE */
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struct vlan_group *vlan_grp;
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u16 num_vlans;
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u8 vlan_tag[VLAN_GROUP_ARRAY_LEN];
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struct be_dma_mem mc_cmd_mem;
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struct be_stats_obj stats;
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/* Work queue used to perform periodic tasks like getting statistics */
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struct delayed_work work;
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/* Ethtool knobs and info */
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bool rx_csum; /* BE card must perform rx-checksumming */
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char fw_ver[FW_VER_LEN];
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u32 if_handle; /* Used to configure filtering */
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u32 pmac_id; /* MAC addr handle used by BE card */
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bool link_up;
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u32 port_num;
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bool promiscuous;
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bool wol;
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u32 cap;
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u32 rx_fc; /* Rx flow control */
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u32 tx_fc; /* Tx flow control */
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int link_speed;
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u8 port_type;
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u8 transceiver;
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};
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extern const struct ethtool_ops be_ethtool_ops;
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#define drvr_stats(adapter) (&adapter->stats.drvr_stats)
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static inline unsigned int be_pci_func(struct be_adapter *adapter)
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{
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return PCI_FUNC(adapter->pdev->devfn);
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}
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#define BE_SET_NETDEV_OPS(netdev, ops) (netdev->netdev_ops = ops)
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#define PAGE_SHIFT_4K 12
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#define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
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/* Returns number of pages spanned by the data starting at the given addr */
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#define PAGES_4K_SPANNED(_address, size) \
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((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
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(size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
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/* Byte offset into the page corresponding to given address */
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#define OFFSET_IN_PAGE(addr) \
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((size_t)(addr) & (PAGE_SIZE_4K-1))
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/* Returns bit offset within a DWORD of a bitfield */
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#define AMAP_BIT_OFFSET(_struct, field) \
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(((size_t)&(((_struct *)0)->field))%32)
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/* Returns the bit mask of the field that is NOT shifted into location. */
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static inline u32 amap_mask(u32 bitsize)
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{
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return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
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}
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static inline void
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amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
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{
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u32 *dw = (u32 *) ptr + dw_offset;
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*dw &= ~(mask << offset);
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*dw |= (mask & value) << offset;
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}
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#define AMAP_SET_BITS(_struct, field, ptr, val) \
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amap_set(ptr, \
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offsetof(_struct, field)/32, \
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amap_mask(sizeof(((_struct *)0)->field)), \
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AMAP_BIT_OFFSET(_struct, field), \
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val)
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static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
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{
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u32 *dw = (u32 *) ptr;
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return mask & (*(dw + dw_offset) >> offset);
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}
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#define AMAP_GET_BITS(_struct, field, ptr) \
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amap_get(ptr, \
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offsetof(_struct, field)/32, \
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amap_mask(sizeof(((_struct *)0)->field)), \
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AMAP_BIT_OFFSET(_struct, field))
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#define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len)
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#define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len)
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static inline void swap_dws(void *wrb, int len)
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{
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#ifdef __BIG_ENDIAN
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u32 *dw = wrb;
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BUG_ON(len % 4);
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do {
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*dw = cpu_to_le32(*dw);
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dw++;
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len -= 4;
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} while (len);
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#endif /* __BIG_ENDIAN */
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}
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static inline u8 is_tcp_pkt(struct sk_buff *skb)
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{
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u8 val = 0;
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if (ip_hdr(skb)->version == 4)
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val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
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else if (ip_hdr(skb)->version == 6)
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val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);
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return val;
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}
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static inline u8 is_udp_pkt(struct sk_buff *skb)
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{
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u8 val = 0;
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if (ip_hdr(skb)->version == 4)
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val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
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else if (ip_hdr(skb)->version == 6)
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val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);
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return val;
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}
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extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm,
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u16 num_popped);
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extern void be_link_status_update(struct be_adapter *adapter, bool link_up);
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extern void netdev_stats_update(struct be_adapter *adapter);
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extern int be_load_fw(struct be_adapter *adapter, u8 *func);
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#endif /* BE_H */
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