569 lines
21 KiB
C
569 lines
21 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Linux/PA-RISC Project (http://www.parisc-linux.org/)
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*
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* Floating-point emulation code
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* Copyright (C) 2001 Hewlett-Packard (Paul Bame) <bame@debian.org>
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*/
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/*
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* BEGIN_DESC
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*
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* File:
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* @(#) pa/spmath/float.h $Revision: 1.1 $
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*
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* Purpose:
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* <<please update with a synopis of the functionality provided by this file>>
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*
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* BE header: no
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*
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* Shipped: yes
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* /usr/conf/pa/spmath/float.h
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*
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* END_DESC
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*/
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#ifdef __NO_PA_HDRS
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PA header file -- do not include this header file for non-PA builds.
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#endif
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#include "fpbits.h"
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#include "hppa.h"
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/*
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* Want to pick up the FPU capability flags, not the PDC structures.
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* 'LOCORE' isn't really true in this case, but we don't want the C structures
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* so it suits our purposes
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*/
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#define LOCORE
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#include "fpu.h"
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/*
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* Declare the basic structures for the 3 different
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* floating-point precisions.
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*
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* Single number
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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* |s| exp | mantissa |
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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*/
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#define Sall(object) (object)
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#define Ssign(object) Bitfield_extract( 0, 1,object)
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#define Ssignedsign(object) Bitfield_signed_extract( 0, 1,object)
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#define Sexponent(object) Bitfield_extract( 1, 8,object)
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#define Smantissa(object) Bitfield_mask( 9, 23,object)
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#define Ssignaling(object) Bitfield_extract( 9, 1,object)
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#define Ssignalingnan(object) Bitfield_extract( 1, 9,object)
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#define Shigh2mantissa(object) Bitfield_extract( 9, 2,object)
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#define Sexponentmantissa(object) Bitfield_mask( 1, 31,object)
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#define Ssignexponent(object) Bitfield_extract( 0, 9,object)
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#define Shidden(object) Bitfield_extract( 8, 1,object)
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#define Shiddenoverflow(object) Bitfield_extract( 7, 1,object)
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#define Shiddenhigh7mantissa(object) Bitfield_extract( 8, 8,object)
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#define Shiddenhigh3mantissa(object) Bitfield_extract( 8, 4,object)
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#define Slow(object) Bitfield_mask( 31, 1,object)
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#define Slow4(object) Bitfield_mask( 28, 4,object)
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#define Slow31(object) Bitfield_mask( 1, 31,object)
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#define Shigh31(object) Bitfield_extract( 0, 31,object)
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#define Ssignedhigh31(object) Bitfield_signed_extract( 0, 31,object)
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#define Shigh4(object) Bitfield_extract( 0, 4,object)
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#define Sbit24(object) Bitfield_extract( 24, 1,object)
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#define Sbit28(object) Bitfield_extract( 28, 1,object)
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#define Sbit29(object) Bitfield_extract( 29, 1,object)
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#define Sbit30(object) Bitfield_extract( 30, 1,object)
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#define Sbit31(object) Bitfield_mask( 31, 1,object)
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#define Deposit_ssign(object,value) Bitfield_deposit(value,0,1,object)
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#define Deposit_sexponent(object,value) Bitfield_deposit(value,1,8,object)
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#define Deposit_smantissa(object,value) Bitfield_deposit(value,9,23,object)
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#define Deposit_shigh2mantissa(object,value) Bitfield_deposit(value,9,2,object)
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#define Deposit_sexponentmantissa(object,value) \
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Bitfield_deposit(value,1,31,object)
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#define Deposit_ssignexponent(object,value) Bitfield_deposit(value,0,9,object)
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#define Deposit_slow(object,value) Bitfield_deposit(value,31,1,object)
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#define Deposit_shigh4(object,value) Bitfield_deposit(value,0,4,object)
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#define Is_ssign(object) Bitfield_mask( 0, 1,object)
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#define Is_ssignaling(object) Bitfield_mask( 9, 1,object)
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#define Is_shidden(object) Bitfield_mask( 8, 1,object)
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#define Is_shiddenoverflow(object) Bitfield_mask( 7, 1,object)
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#define Is_slow(object) Bitfield_mask( 31, 1,object)
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#define Is_sbit24(object) Bitfield_mask( 24, 1,object)
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#define Is_sbit28(object) Bitfield_mask( 28, 1,object)
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#define Is_sbit29(object) Bitfield_mask( 29, 1,object)
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#define Is_sbit30(object) Bitfield_mask( 30, 1,object)
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#define Is_sbit31(object) Bitfield_mask( 31, 1,object)
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/*
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* Double number.
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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* |s| exponent | mantissa part 1 |
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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*
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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* | mantissa part 2 |
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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*/
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#define Dallp1(object) (object)
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#define Dsign(object) Bitfield_extract( 0, 1,object)
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#define Dsignedsign(object) Bitfield_signed_extract( 0, 1,object)
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#define Dexponent(object) Bitfield_extract( 1, 11,object)
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#define Dmantissap1(object) Bitfield_mask( 12, 20,object)
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#define Dsignaling(object) Bitfield_extract( 12, 1,object)
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#define Dsignalingnan(object) Bitfield_extract( 1, 12,object)
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#define Dhigh2mantissa(object) Bitfield_extract( 12, 2,object)
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#define Dexponentmantissap1(object) Bitfield_mask( 1, 31,object)
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#define Dsignexponent(object) Bitfield_extract( 0, 12,object)
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#define Dhidden(object) Bitfield_extract( 11, 1,object)
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#define Dhiddenoverflow(object) Bitfield_extract( 10, 1,object)
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#define Dhiddenhigh7mantissa(object) Bitfield_extract( 11, 8,object)
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#define Dhiddenhigh3mantissa(object) Bitfield_extract( 11, 4,object)
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#define Dlowp1(object) Bitfield_mask( 31, 1,object)
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#define Dlow31p1(object) Bitfield_mask( 1, 31,object)
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#define Dhighp1(object) Bitfield_extract( 0, 1,object)
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#define Dhigh4p1(object) Bitfield_extract( 0, 4,object)
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#define Dhigh31p1(object) Bitfield_extract( 0, 31,object)
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#define Dsignedhigh31p1(object) Bitfield_signed_extract( 0, 31,object)
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#define Dbit3p1(object) Bitfield_extract( 3, 1,object)
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#define Deposit_dsign(object,value) Bitfield_deposit(value,0,1,object)
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#define Deposit_dexponent(object,value) Bitfield_deposit(value,1,11,object)
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#define Deposit_dmantissap1(object,value) Bitfield_deposit(value,12,20,object)
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#define Deposit_dhigh2mantissa(object,value) Bitfield_deposit(value,12,2,object)
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#define Deposit_dexponentmantissap1(object,value) \
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Bitfield_deposit(value,1,31,object)
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#define Deposit_dsignexponent(object,value) Bitfield_deposit(value,0,12,object)
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#define Deposit_dlowp1(object,value) Bitfield_deposit(value,31,1,object)
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#define Deposit_dhigh4p1(object,value) Bitfield_deposit(value,0,4,object)
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#define Is_dsign(object) Bitfield_mask( 0, 1,object)
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#define Is_dsignaling(object) Bitfield_mask( 12, 1,object)
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#define Is_dhidden(object) Bitfield_mask( 11, 1,object)
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#define Is_dhiddenoverflow(object) Bitfield_mask( 10, 1,object)
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#define Is_dlowp1(object) Bitfield_mask( 31, 1,object)
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#define Is_dhighp1(object) Bitfield_mask( 0, 1,object)
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#define Is_dbit3p1(object) Bitfield_mask( 3, 1,object)
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#define Dallp2(object) (object)
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#define Dmantissap2(object) (object)
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#define Dlowp2(object) Bitfield_mask( 31, 1,object)
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#define Dlow4p2(object) Bitfield_mask( 28, 4,object)
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#define Dlow31p2(object) Bitfield_mask( 1, 31,object)
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#define Dhighp2(object) Bitfield_extract( 0, 1,object)
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#define Dhigh31p2(object) Bitfield_extract( 0, 31,object)
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#define Dbit2p2(object) Bitfield_extract( 2, 1,object)
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#define Dbit3p2(object) Bitfield_extract( 3, 1,object)
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#define Dbit21p2(object) Bitfield_extract( 21, 1,object)
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#define Dbit28p2(object) Bitfield_extract( 28, 1,object)
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#define Dbit29p2(object) Bitfield_extract( 29, 1,object)
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#define Dbit30p2(object) Bitfield_extract( 30, 1,object)
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#define Dbit31p2(object) Bitfield_mask( 31, 1,object)
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#define Deposit_dlowp2(object,value) Bitfield_deposit(value,31,1,object)
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#define Is_dlowp2(object) Bitfield_mask( 31, 1,object)
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#define Is_dhighp2(object) Bitfield_mask( 0, 1,object)
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#define Is_dbit2p2(object) Bitfield_mask( 2, 1,object)
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#define Is_dbit3p2(object) Bitfield_mask( 3, 1,object)
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#define Is_dbit21p2(object) Bitfield_mask( 21, 1,object)
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#define Is_dbit28p2(object) Bitfield_mask( 28, 1,object)
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#define Is_dbit29p2(object) Bitfield_mask( 29, 1,object)
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#define Is_dbit30p2(object) Bitfield_mask( 30, 1,object)
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#define Is_dbit31p2(object) Bitfield_mask( 31, 1,object)
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/*
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* Quad number.
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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* |s| exponent | mantissa part 1 |
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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*
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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* | mantissa part 2 |
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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*
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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* | mantissa part 3 |
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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*
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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* | mantissa part 4 |
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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*/
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typedef struct
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{
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union
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{
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struct { unsigned qallp1; } u_qallp1;
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/* Not needed for now...
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Bitfield_extract( 0, 1,u_qsign,qsign)
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Bitfield_signed_extract( 0, 1,u_qsignedsign,qsignedsign)
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Bitfield_extract( 1, 15,u_qexponent,qexponent)
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Bitfield_extract(16, 16,u_qmantissap1,qmantissap1)
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Bitfield_extract(16, 1,u_qsignaling,qsignaling)
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Bitfield_extract(1, 16,u_qsignalingnan,qsignalingnan)
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Bitfield_extract(16, 2,u_qhigh2mantissa,qhigh2mantissa)
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Bitfield_extract( 1, 31,u_qexponentmantissap1,qexponentmantissap1)
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Bitfield_extract( 0, 16,u_qsignexponent,qsignexponent)
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Bitfield_extract(15, 1,u_qhidden,qhidden)
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Bitfield_extract(14, 1,u_qhiddenoverflow,qhiddenoverflow)
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Bitfield_extract(15, 8,u_qhiddenhigh7mantissa,qhiddenhigh7mantissa)
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Bitfield_extract(15, 4,u_qhiddenhigh3mantissa,qhiddenhigh3mantissa)
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Bitfield_extract(31, 1,u_qlowp1,qlowp1)
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Bitfield_extract( 1, 31,u_qlow31p1,qlow31p1)
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Bitfield_extract( 0, 1,u_qhighp1,qhighp1)
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Bitfield_extract( 0, 4,u_qhigh4p1,qhigh4p1)
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Bitfield_extract( 0, 31,u_qhigh31p1,qhigh31p1)
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*/
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} quad_u1;
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union
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{
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struct { unsigned qallp2; } u_qallp2;
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/* Not needed for now...
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Bitfield_extract(31, 1,u_qlowp2,qlowp2)
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Bitfield_extract( 1, 31,u_qlow31p2,qlow31p2)
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Bitfield_extract( 0, 1,u_qhighp2,qhighp2)
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Bitfield_extract( 0, 31,u_qhigh31p2,qhigh31p2)
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*/
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} quad_u2;
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union
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{
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struct { unsigned qallp3; } u_qallp3;
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/* Not needed for now...
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Bitfield_extract(31, 1,u_qlowp3,qlowp3)
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Bitfield_extract( 1, 31,u_qlow31p3,qlow31p3)
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Bitfield_extract( 0, 1,u_qhighp3,qhighp3)
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Bitfield_extract( 0, 31,u_qhigh31p3,qhigh31p3)
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*/
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} quad_u3;
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union
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{
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struct { unsigned qallp4; } u_qallp4;
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/* Not need for now...
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Bitfield_extract(31, 1,u_qlowp4,qlowp4)
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Bitfield_extract( 1, 31,u_qlow31p4,qlow31p4)
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Bitfield_extract( 0, 1,u_qhighp4,qhighp4)
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Bitfield_extract( 0, 31,u_qhigh31p4,qhigh31p4)
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*/
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} quad_u4;
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} quad_floating_point;
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/* Extension - An additional structure to hold the guard, round and
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* sticky bits during computations.
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*/
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#define Extall(object) (object)
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#define Extsign(object) Bitfield_extract( 0, 1,object)
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#define Exthigh31(object) Bitfield_extract( 0, 31,object)
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#define Extlow31(object) Bitfield_extract( 1, 31,object)
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#define Extlow(object) Bitfield_extract( 31, 1,object)
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/*
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* Single extended - The upper word is just like single precision,
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* but one additional word of mantissa is needed.
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*/
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#define Sextallp1(object) (object)
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#define Sextallp2(object) (object)
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#define Sextlowp1(object) Bitfield_extract( 31, 1,object)
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#define Sexthighp2(object) Bitfield_extract( 0, 1,object)
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#define Sextlow31p2(object) Bitfield_extract( 1, 31,object)
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#define Sexthiddenoverflow(object) Bitfield_extract( 4, 1,object)
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#define Is_sexthiddenoverflow(object) Bitfield_mask( 4, 1,object)
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/*
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* Double extended - The upper two words are just like double precision,
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* but two additional words of mantissa are needed.
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*/
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#define Dextallp1(object) (object)
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#define Dextallp2(object) (object)
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#define Dextallp3(object) (object)
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#define Dextallp4(object) (object)
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#define Dextlowp2(object) Bitfield_extract( 31, 1,object)
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#define Dexthighp3(object) Bitfield_extract( 0, 1,object)
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#define Dextlow31p3(object) Bitfield_extract( 1, 31,object)
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#define Dexthiddenoverflow(object) Bitfield_extract( 10, 1,object)
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#define Is_dexthiddenoverflow(object) Bitfield_mask( 10, 1,object)
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#define Deposit_dextlowp4(object,value) Bitfield_deposit(value,31,1,object)
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/*
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* Declare the basic structures for the 3 different
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* fixed-point precisions.
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*
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* Single number
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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* |s| integer |
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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*/
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typedef int sgl_integer;
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/*
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* Double number.
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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* |s| high integer |
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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*
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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* | low integer |
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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*/
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struct dint {
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int wd0;
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unsigned int wd1;
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};
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struct dblwd {
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unsigned int wd0;
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unsigned int wd1;
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};
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/*
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* Quad number.
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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* |s| integer part1 |
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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*
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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* | integer part 2 |
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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*
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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* | integer part 3 |
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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*
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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* | integer part 4 |
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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*/
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struct quadwd {
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int wd0;
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unsigned int wd1;
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unsigned int wd2;
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unsigned int wd3;
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};
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typedef struct quadwd quad_integer;
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/* useful typedefs */
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typedef unsigned int sgl_floating_point;
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typedef struct dblwd dbl_floating_point;
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typedef struct dint dbl_integer;
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typedef struct dblwd dbl_unsigned;
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/*
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* Define the different precisions' parameters.
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*/
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#define SGL_BITLENGTH 32
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#define SGL_EMAX 127
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#define SGL_EMIN (-126)
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#define SGL_BIAS 127
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#define SGL_WRAP 192
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#define SGL_INFINITY_EXPONENT (SGL_EMAX+SGL_BIAS+1)
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#define SGL_THRESHOLD 32
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#define SGL_EXP_LENGTH 8
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#define SGL_P 24
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#define DBL_BITLENGTH 64
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#define DBL_EMAX 1023
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#define DBL_EMIN (-1022)
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#define DBL_BIAS 1023
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#define DBL_WRAP 1536
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#define DBL_INFINITY_EXPONENT (DBL_EMAX+DBL_BIAS+1)
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#define DBL_THRESHOLD 64
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#define DBL_EXP_LENGTH 11
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#define DBL_P 53
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#define QUAD_BITLENGTH 128
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#define QUAD_EMAX 16383
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#define QUAD_EMIN (-16382)
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#define QUAD_BIAS 16383
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#define QUAD_WRAP 24576
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#define QUAD_INFINITY_EXPONENT (QUAD_EMAX+QUAD_BIAS+1)
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#define QUAD_P 113
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/* Boolean Values etc. */
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#define FALSE 0
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#define TRUE (!FALSE)
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#define NOT !
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#define XOR ^
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/* other constants */
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#undef NULL
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#define NULL 0
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#define NIL 0
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#define SGL 0
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#define DBL 1
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#define BADFMT 2
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#define QUAD 3
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/* Types */
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typedef int boolean;
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typedef int FORMAT;
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typedef int VOID;
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/* Declare status register equivalent to FPUs architecture.
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*
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* 0 1 2 3 4 5 6 7 8 910 1 2 3 4 5 6 7 8 920 1 2 3 4 5 6 7 8 930 1
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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* |V|Z|O|U|I|C| rsv | model | version |RM |rsv|T|r|V|Z|O|U|I|
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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*/
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#define Cbit(object) Bitfield_extract( 5, 1,object)
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#define Tbit(object) Bitfield_extract( 25, 1,object)
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#define Roundingmode(object) Bitfield_extract( 21, 2,object)
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#define Invalidtrap(object) Bitfield_extract( 27, 1,object)
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#define Divisionbyzerotrap(object) Bitfield_extract( 28, 1,object)
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#define Overflowtrap(object) Bitfield_extract( 29, 1,object)
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#define Underflowtrap(object) Bitfield_extract( 30, 1,object)
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#define Inexacttrap(object) Bitfield_extract( 31, 1,object)
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#define Invalidflag(object) Bitfield_extract( 0, 1,object)
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#define Divisionbyzeroflag(object) Bitfield_extract( 1, 1,object)
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#define Overflowflag(object) Bitfield_extract( 2, 1,object)
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#define Underflowflag(object) Bitfield_extract( 3, 1,object)
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#define Inexactflag(object) Bitfield_extract( 4, 1,object)
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#define Allflags(object) Bitfield_extract( 0, 5,object)
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/* Definitions relevant to the status register */
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/* Rounding Modes */
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#define ROUNDNEAREST 0
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#define ROUNDZERO 1
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#define ROUNDPLUS 2
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#define ROUNDMINUS 3
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/* Exceptions */
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#define NOEXCEPTION 0x0
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#define INVALIDEXCEPTION 0x20
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#define DIVISIONBYZEROEXCEPTION 0x10
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#define OVERFLOWEXCEPTION 0x08
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#define UNDERFLOWEXCEPTION 0x04
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#define INEXACTEXCEPTION 0x02
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#define UNIMPLEMENTEDEXCEPTION 0x01
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/* New exceptions for the 2E Opcode */
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#define OPC_2E_INVALIDEXCEPTION 0x30
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#define OPC_2E_OVERFLOWEXCEPTION 0x18
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#define OPC_2E_UNDERFLOWEXCEPTION 0x0c
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#define OPC_2E_INEXACTEXCEPTION 0x12
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/* Declare exception registers equivalent to FPUs architecture
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*
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* 0 1 2 3 4 5 6 7 8 910 1 2 3 4 5 6 7 8 920 1 2 3 4 5 6 7 8 930 1
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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* |excepttype | r1 | r2/ext | operation |parm |n| t/cond |
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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*/
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#define Allexception(object) (object)
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#define Exceptiontype(object) Bitfield_extract( 0, 6,object)
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#define Instructionfield(object) Bitfield_mask( 6,26,object)
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#define Parmfield(object) Bitfield_extract( 23, 3,object)
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#define Rabit(object) Bitfield_extract( 24, 1,object)
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#define Ibit(object) Bitfield_extract( 25, 1,object)
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#define Set_exceptiontype(object,value) Bitfield_deposit(value, 0, 6,object)
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#define Set_parmfield(object,value) Bitfield_deposit(value, 23, 3,object)
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#define Set_exceptiontype_and_instr_field(exception,instruction,object) \
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object = exception << 26 | instruction
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/* Declare the condition field
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*
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* 0 1 2 3 4 5 6 7 8 910 1 2 3 4 5 6 7 8 920 1 2 3 4 5 6 7 8 930 1
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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* | |G|L|E|U|X|
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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*/
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#define Greaterthanbit(object) Bitfield_extract( 27, 1,object)
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#define Lessthanbit(object) Bitfield_extract( 28, 1,object)
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#define Equalbit(object) Bitfield_extract( 29, 1,object)
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#define Unorderedbit(object) Bitfield_extract( 30, 1,object)
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#define Exceptionbit(object) Bitfield_extract( 31, 1,object)
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/* An alias name for the status register */
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#define Fpustatus_register (*status)
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/**************************************************
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* Status register referencing and manipulation. *
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**************************************************/
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/* Rounding mode */
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#define Rounding_mode() Roundingmode(Fpustatus_register)
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#define Is_rounding_mode(rmode) \
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(Roundingmode(Fpustatus_register) == rmode)
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#define Set_rounding_mode(value) \
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Bitfield_deposit(value,21,2,Fpustatus_register)
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/* Boolean testing of the trap enable bits */
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#define Is_invalidtrap_enabled() Invalidtrap(Fpustatus_register)
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#define Is_divisionbyzerotrap_enabled() Divisionbyzerotrap(Fpustatus_register)
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#define Is_overflowtrap_enabled() Overflowtrap(Fpustatus_register)
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#define Is_underflowtrap_enabled() Underflowtrap(Fpustatus_register)
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#define Is_inexacttrap_enabled() Inexacttrap(Fpustatus_register)
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/* Set the indicated flags in the status register */
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#define Set_invalidflag() Bitfield_deposit(1,0,1,Fpustatus_register)
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#define Set_divisionbyzeroflag() Bitfield_deposit(1,1,1,Fpustatus_register)
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#define Set_overflowflag() Bitfield_deposit(1,2,1,Fpustatus_register)
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#define Set_underflowflag() Bitfield_deposit(1,3,1,Fpustatus_register)
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#define Set_inexactflag() Bitfield_deposit(1,4,1,Fpustatus_register)
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|
|
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#define Clear_all_flags() Bitfield_deposit(0,0,5,Fpustatus_register)
|
|
|
|
/* Manipulate the trap and condition code bits (tbit and cbit) */
|
|
#define Set_tbit() Bitfield_deposit(1,25,1,Fpustatus_register)
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#define Clear_tbit() Bitfield_deposit(0,25,1,Fpustatus_register)
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#define Is_tbit_set() Tbit(Fpustatus_register)
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|
#define Is_cbit_set() Cbit(Fpustatus_register)
|
|
|
|
#define Set_status_cbit(value) \
|
|
Bitfield_deposit(value,5,1,Fpustatus_register)
|
|
|
|
/*******************************
|
|
* Condition field referencing *
|
|
*******************************/
|
|
#define Unordered(cond) Unorderedbit(cond)
|
|
#define Equal(cond) Equalbit(cond)
|
|
#define Lessthan(cond) Lessthanbit(cond)
|
|
#define Greaterthan(cond) Greaterthanbit(cond)
|
|
#define Exception(cond) Exceptionbit(cond)
|
|
|
|
|
|
/* Defines for the extension */
|
|
#define Ext_isone_sign(extent) (Extsign(extent))
|
|
#define Ext_isnotzero(extent) \
|
|
(Extall(extent))
|
|
#define Ext_isnotzero_lower(extent) \
|
|
(Extlow31(extent))
|
|
#define Ext_leftshiftby1(extent) \
|
|
Extall(extent) <<= 1
|
|
#define Ext_negate(extent) \
|
|
(int )Extall(extent) = 0 - (int )Extall(extent)
|
|
#define Ext_setone_low(extent) Bitfield_deposit(1,31,1,extent)
|
|
#define Ext_setzero(extent) Extall(extent) = 0
|
|
|
|
typedef int operation;
|
|
|
|
/* error messages */
|
|
|
|
#define NONE 0
|
|
#define UNDEFFPINST 1
|
|
|
|
/* Function definitions: opcode, opclass */
|
|
#define FTEST (1<<2) | 0
|
|
#define FCPY (2<<2) | 0
|
|
#define FABS (3<<2) | 0
|
|
#define FSQRT (4<<2) | 0
|
|
#define FRND (5<<2) | 0
|
|
|
|
#define FCNVFF (0<<2) | 1
|
|
#define FCNVXF (1<<2) | 1
|
|
#define FCNVFX (2<<2) | 1
|
|
#define FCNVFXT (3<<2) | 1
|
|
|
|
#define FCMP (0<<2) | 2
|
|
|
|
#define FADD (0<<2) | 3
|
|
#define FSUB (1<<2) | 3
|
|
#define FMPY (2<<2) | 3
|
|
#define FDIV (3<<2) | 3
|
|
#define FREM (4<<2) | 3
|
|
|