748 lines
17 KiB
C
748 lines
17 KiB
C
/*
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* Copyright (C) 2011-2014 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <linux/iommu.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <soc/tegra/ahb.h>
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#include <soc/tegra/mc.h>
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struct tegra_smmu {
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void __iomem *regs;
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struct device *dev;
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struct tegra_mc *mc;
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const struct tegra_smmu_soc *soc;
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unsigned long pfn_mask;
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unsigned long *asids;
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struct mutex lock;
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struct list_head list;
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};
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struct tegra_smmu_as {
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struct iommu_domain domain;
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struct tegra_smmu *smmu;
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unsigned int use_count;
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struct page *count;
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struct page *pd;
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unsigned id;
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u32 attr;
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};
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static struct tegra_smmu_as *to_smmu_as(struct iommu_domain *dom)
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{
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return container_of(dom, struct tegra_smmu_as, domain);
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}
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static inline void smmu_writel(struct tegra_smmu *smmu, u32 value,
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unsigned long offset)
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{
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writel(value, smmu->regs + offset);
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}
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static inline u32 smmu_readl(struct tegra_smmu *smmu, unsigned long offset)
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{
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return readl(smmu->regs + offset);
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}
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#define SMMU_CONFIG 0x010
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#define SMMU_CONFIG_ENABLE (1 << 0)
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#define SMMU_TLB_CONFIG 0x14
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#define SMMU_TLB_CONFIG_HIT_UNDER_MISS (1 << 29)
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#define SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION (1 << 28)
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#define SMMU_TLB_CONFIG_ACTIVE_LINES(x) ((x) & 0x3f)
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#define SMMU_PTC_CONFIG 0x18
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#define SMMU_PTC_CONFIG_ENABLE (1 << 29)
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#define SMMU_PTC_CONFIG_REQ_LIMIT(x) (((x) & 0x0f) << 24)
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#define SMMU_PTC_CONFIG_INDEX_MAP(x) ((x) & 0x3f)
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#define SMMU_PTB_ASID 0x01c
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#define SMMU_PTB_ASID_VALUE(x) ((x) & 0x7f)
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#define SMMU_PTB_DATA 0x020
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#define SMMU_PTB_DATA_VALUE(page, attr) (page_to_phys(page) >> 12 | (attr))
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#define SMMU_MK_PDE(page, attr) (page_to_phys(page) >> SMMU_PTE_SHIFT | (attr))
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#define SMMU_TLB_FLUSH 0x030
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#define SMMU_TLB_FLUSH_VA_MATCH_ALL (0 << 0)
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#define SMMU_TLB_FLUSH_VA_MATCH_SECTION (2 << 0)
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#define SMMU_TLB_FLUSH_VA_MATCH_GROUP (3 << 0)
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#define SMMU_TLB_FLUSH_ASID(x) (((x) & 0x7f) << 24)
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#define SMMU_TLB_FLUSH_VA_SECTION(addr) ((((addr) & 0xffc00000) >> 12) | \
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SMMU_TLB_FLUSH_VA_MATCH_SECTION)
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#define SMMU_TLB_FLUSH_VA_GROUP(addr) ((((addr) & 0xffffc000) >> 12) | \
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SMMU_TLB_FLUSH_VA_MATCH_GROUP)
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#define SMMU_TLB_FLUSH_ASID_MATCH (1 << 31)
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#define SMMU_PTC_FLUSH 0x034
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#define SMMU_PTC_FLUSH_TYPE_ALL (0 << 0)
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#define SMMU_PTC_FLUSH_TYPE_ADR (1 << 0)
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#define SMMU_PTC_FLUSH_HI 0x9b8
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#define SMMU_PTC_FLUSH_HI_MASK 0x3
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/* per-SWGROUP SMMU_*_ASID register */
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#define SMMU_ASID_ENABLE (1 << 31)
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#define SMMU_ASID_MASK 0x7f
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#define SMMU_ASID_VALUE(x) ((x) & SMMU_ASID_MASK)
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/* page table definitions */
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#define SMMU_NUM_PDE 1024
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#define SMMU_NUM_PTE 1024
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#define SMMU_SIZE_PD (SMMU_NUM_PDE * 4)
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#define SMMU_SIZE_PT (SMMU_NUM_PTE * 4)
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#define SMMU_PDE_SHIFT 22
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#define SMMU_PTE_SHIFT 12
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#define SMMU_PD_READABLE (1 << 31)
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#define SMMU_PD_WRITABLE (1 << 30)
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#define SMMU_PD_NONSECURE (1 << 29)
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#define SMMU_PDE_READABLE (1 << 31)
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#define SMMU_PDE_WRITABLE (1 << 30)
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#define SMMU_PDE_NONSECURE (1 << 29)
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#define SMMU_PDE_NEXT (1 << 28)
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#define SMMU_PTE_READABLE (1 << 31)
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#define SMMU_PTE_WRITABLE (1 << 30)
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#define SMMU_PTE_NONSECURE (1 << 29)
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#define SMMU_PDE_ATTR (SMMU_PDE_READABLE | SMMU_PDE_WRITABLE | \
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SMMU_PDE_NONSECURE)
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#define SMMU_PTE_ATTR (SMMU_PTE_READABLE | SMMU_PTE_WRITABLE | \
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SMMU_PTE_NONSECURE)
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static inline void smmu_flush_ptc(struct tegra_smmu *smmu, struct page *page,
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unsigned long offset)
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{
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phys_addr_t phys = page ? page_to_phys(page) : 0;
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u32 value;
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if (page) {
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offset &= ~(smmu->mc->soc->atom_size - 1);
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if (smmu->mc->soc->num_address_bits > 32) {
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#ifdef CONFIG_PHYS_ADDR_T_64BIT
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value = (phys >> 32) & SMMU_PTC_FLUSH_HI_MASK;
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#else
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value = 0;
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#endif
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smmu_writel(smmu, value, SMMU_PTC_FLUSH_HI);
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}
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value = (phys + offset) | SMMU_PTC_FLUSH_TYPE_ADR;
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} else {
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value = SMMU_PTC_FLUSH_TYPE_ALL;
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}
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smmu_writel(smmu, value, SMMU_PTC_FLUSH);
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}
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static inline void smmu_flush_tlb(struct tegra_smmu *smmu)
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{
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smmu_writel(smmu, SMMU_TLB_FLUSH_VA_MATCH_ALL, SMMU_TLB_FLUSH);
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}
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static inline void smmu_flush_tlb_asid(struct tegra_smmu *smmu,
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unsigned long asid)
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{
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u32 value;
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value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) |
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SMMU_TLB_FLUSH_VA_MATCH_ALL;
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smmu_writel(smmu, value, SMMU_TLB_FLUSH);
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}
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static inline void smmu_flush_tlb_section(struct tegra_smmu *smmu,
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unsigned long asid,
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unsigned long iova)
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{
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u32 value;
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value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) |
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SMMU_TLB_FLUSH_VA_SECTION(iova);
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smmu_writel(smmu, value, SMMU_TLB_FLUSH);
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}
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static inline void smmu_flush_tlb_group(struct tegra_smmu *smmu,
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unsigned long asid,
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unsigned long iova)
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{
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u32 value;
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value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) |
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SMMU_TLB_FLUSH_VA_GROUP(iova);
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smmu_writel(smmu, value, SMMU_TLB_FLUSH);
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}
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static inline void smmu_flush(struct tegra_smmu *smmu)
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{
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smmu_readl(smmu, SMMU_CONFIG);
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}
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static int tegra_smmu_alloc_asid(struct tegra_smmu *smmu, unsigned int *idp)
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{
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unsigned long id;
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mutex_lock(&smmu->lock);
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id = find_first_zero_bit(smmu->asids, smmu->soc->num_asids);
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if (id >= smmu->soc->num_asids) {
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mutex_unlock(&smmu->lock);
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return -ENOSPC;
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}
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set_bit(id, smmu->asids);
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*idp = id;
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mutex_unlock(&smmu->lock);
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return 0;
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}
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static void tegra_smmu_free_asid(struct tegra_smmu *smmu, unsigned int id)
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{
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mutex_lock(&smmu->lock);
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clear_bit(id, smmu->asids);
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mutex_unlock(&smmu->lock);
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}
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static bool tegra_smmu_capable(enum iommu_cap cap)
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{
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return false;
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}
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static struct iommu_domain *tegra_smmu_domain_alloc(unsigned type)
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{
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struct tegra_smmu_as *as;
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unsigned int i;
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uint32_t *pd;
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if (type != IOMMU_DOMAIN_UNMANAGED)
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return NULL;
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as = kzalloc(sizeof(*as), GFP_KERNEL);
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if (!as)
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return NULL;
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as->attr = SMMU_PD_READABLE | SMMU_PD_WRITABLE | SMMU_PD_NONSECURE;
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as->pd = alloc_page(GFP_KERNEL | __GFP_DMA);
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if (!as->pd) {
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kfree(as);
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return NULL;
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}
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as->count = alloc_page(GFP_KERNEL);
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if (!as->count) {
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__free_page(as->pd);
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kfree(as);
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return NULL;
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}
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/* clear PDEs */
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pd = page_address(as->pd);
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SetPageReserved(as->pd);
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for (i = 0; i < SMMU_NUM_PDE; i++)
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pd[i] = 0;
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/* clear PDE usage counters */
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pd = page_address(as->count);
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SetPageReserved(as->count);
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for (i = 0; i < SMMU_NUM_PDE; i++)
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pd[i] = 0;
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/* setup aperture */
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as->domain.geometry.aperture_start = 0;
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as->domain.geometry.aperture_end = 0xffffffff;
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as->domain.geometry.force_aperture = true;
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return &as->domain;
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}
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static void tegra_smmu_domain_free(struct iommu_domain *domain)
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{
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struct tegra_smmu_as *as = to_smmu_as(domain);
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/* TODO: free page directory and page tables */
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ClearPageReserved(as->pd);
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kfree(as);
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}
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static const struct tegra_smmu_swgroup *
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tegra_smmu_find_swgroup(struct tegra_smmu *smmu, unsigned int swgroup)
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{
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const struct tegra_smmu_swgroup *group = NULL;
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unsigned int i;
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for (i = 0; i < smmu->soc->num_swgroups; i++) {
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if (smmu->soc->swgroups[i].swgroup == swgroup) {
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group = &smmu->soc->swgroups[i];
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break;
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}
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}
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return group;
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}
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static void tegra_smmu_enable(struct tegra_smmu *smmu, unsigned int swgroup,
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unsigned int asid)
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{
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const struct tegra_smmu_swgroup *group;
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unsigned int i;
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u32 value;
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for (i = 0; i < smmu->soc->num_clients; i++) {
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const struct tegra_mc_client *client = &smmu->soc->clients[i];
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if (client->swgroup != swgroup)
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continue;
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value = smmu_readl(smmu, client->smmu.reg);
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value |= BIT(client->smmu.bit);
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smmu_writel(smmu, value, client->smmu.reg);
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}
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group = tegra_smmu_find_swgroup(smmu, swgroup);
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if (group) {
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value = smmu_readl(smmu, group->reg);
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value &= ~SMMU_ASID_MASK;
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value |= SMMU_ASID_VALUE(asid);
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value |= SMMU_ASID_ENABLE;
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smmu_writel(smmu, value, group->reg);
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}
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}
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static void tegra_smmu_disable(struct tegra_smmu *smmu, unsigned int swgroup,
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unsigned int asid)
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{
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const struct tegra_smmu_swgroup *group;
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unsigned int i;
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u32 value;
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group = tegra_smmu_find_swgroup(smmu, swgroup);
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if (group) {
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value = smmu_readl(smmu, group->reg);
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value &= ~SMMU_ASID_MASK;
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value |= SMMU_ASID_VALUE(asid);
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value &= ~SMMU_ASID_ENABLE;
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smmu_writel(smmu, value, group->reg);
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}
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for (i = 0; i < smmu->soc->num_clients; i++) {
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const struct tegra_mc_client *client = &smmu->soc->clients[i];
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if (client->swgroup != swgroup)
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continue;
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value = smmu_readl(smmu, client->smmu.reg);
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value &= ~BIT(client->smmu.bit);
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smmu_writel(smmu, value, client->smmu.reg);
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}
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}
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static int tegra_smmu_as_prepare(struct tegra_smmu *smmu,
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struct tegra_smmu_as *as)
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{
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u32 value;
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int err;
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if (as->use_count > 0) {
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as->use_count++;
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return 0;
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}
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err = tegra_smmu_alloc_asid(smmu, &as->id);
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if (err < 0)
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return err;
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smmu->soc->ops->flush_dcache(as->pd, 0, SMMU_SIZE_PD);
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smmu_flush_ptc(smmu, as->pd, 0);
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smmu_flush_tlb_asid(smmu, as->id);
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smmu_writel(smmu, as->id & 0x7f, SMMU_PTB_ASID);
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value = SMMU_PTB_DATA_VALUE(as->pd, as->attr);
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smmu_writel(smmu, value, SMMU_PTB_DATA);
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smmu_flush(smmu);
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as->smmu = smmu;
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as->use_count++;
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return 0;
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}
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static void tegra_smmu_as_unprepare(struct tegra_smmu *smmu,
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struct tegra_smmu_as *as)
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{
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if (--as->use_count > 0)
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return;
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tegra_smmu_free_asid(smmu, as->id);
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as->smmu = NULL;
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}
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static int tegra_smmu_attach_dev(struct iommu_domain *domain,
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struct device *dev)
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{
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struct tegra_smmu *smmu = dev->archdata.iommu;
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struct tegra_smmu_as *as = to_smmu_as(domain);
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struct device_node *np = dev->of_node;
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struct of_phandle_args args;
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unsigned int index = 0;
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int err = 0;
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while (!of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index,
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&args)) {
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unsigned int swgroup = args.args[0];
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if (args.np != smmu->dev->of_node) {
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of_node_put(args.np);
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continue;
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}
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of_node_put(args.np);
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err = tegra_smmu_as_prepare(smmu, as);
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if (err < 0)
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return err;
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tegra_smmu_enable(smmu, swgroup, as->id);
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index++;
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}
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if (index == 0)
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return -ENODEV;
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return 0;
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}
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static void tegra_smmu_detach_dev(struct iommu_domain *domain, struct device *dev)
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{
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struct tegra_smmu_as *as = to_smmu_as(domain);
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struct device_node *np = dev->of_node;
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struct tegra_smmu *smmu = as->smmu;
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struct of_phandle_args args;
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unsigned int index = 0;
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while (!of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index,
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&args)) {
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unsigned int swgroup = args.args[0];
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if (args.np != smmu->dev->of_node) {
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of_node_put(args.np);
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continue;
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}
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of_node_put(args.np);
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tegra_smmu_disable(smmu, swgroup, as->id);
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tegra_smmu_as_unprepare(smmu, as);
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index++;
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}
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}
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static u32 *as_get_pte(struct tegra_smmu_as *as, dma_addr_t iova,
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struct page **pagep)
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{
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u32 *pd = page_address(as->pd), *pt, *count;
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u32 pde = (iova >> SMMU_PDE_SHIFT) & 0x3ff;
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u32 pte = (iova >> SMMU_PTE_SHIFT) & 0x3ff;
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struct tegra_smmu *smmu = as->smmu;
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struct page *page;
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unsigned int i;
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if (pd[pde] == 0) {
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page = alloc_page(GFP_KERNEL | __GFP_DMA);
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if (!page)
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return NULL;
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pt = page_address(page);
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SetPageReserved(page);
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for (i = 0; i < SMMU_NUM_PTE; i++)
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pt[i] = 0;
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smmu->soc->ops->flush_dcache(page, 0, SMMU_SIZE_PT);
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pd[pde] = SMMU_MK_PDE(page, SMMU_PDE_ATTR | SMMU_PDE_NEXT);
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smmu->soc->ops->flush_dcache(as->pd, pde << 2, 4);
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smmu_flush_ptc(smmu, as->pd, pde << 2);
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smmu_flush_tlb_section(smmu, as->id, iova);
|
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smmu_flush(smmu);
|
|
} else {
|
|
page = pfn_to_page(pd[pde] & smmu->pfn_mask);
|
|
pt = page_address(page);
|
|
}
|
|
|
|
*pagep = page;
|
|
|
|
/* Keep track of entries in this page table. */
|
|
count = page_address(as->count);
|
|
if (pt[pte] == 0)
|
|
count[pde]++;
|
|
|
|
return &pt[pte];
|
|
}
|
|
|
|
static void as_put_pte(struct tegra_smmu_as *as, dma_addr_t iova)
|
|
{
|
|
u32 pde = (iova >> SMMU_PDE_SHIFT) & 0x3ff;
|
|
u32 pte = (iova >> SMMU_PTE_SHIFT) & 0x3ff;
|
|
u32 *count = page_address(as->count);
|
|
u32 *pd = page_address(as->pd), *pt;
|
|
struct page *page;
|
|
|
|
page = pfn_to_page(pd[pde] & as->smmu->pfn_mask);
|
|
pt = page_address(page);
|
|
|
|
/*
|
|
* When no entries in this page table are used anymore, return the
|
|
* memory page to the system.
|
|
*/
|
|
if (pt[pte] != 0) {
|
|
if (--count[pde] == 0) {
|
|
ClearPageReserved(page);
|
|
__free_page(page);
|
|
pd[pde] = 0;
|
|
}
|
|
|
|
pt[pte] = 0;
|
|
}
|
|
}
|
|
|
|
static int tegra_smmu_map(struct iommu_domain *domain, unsigned long iova,
|
|
phys_addr_t paddr, size_t size, int prot)
|
|
{
|
|
struct tegra_smmu_as *as = to_smmu_as(domain);
|
|
struct tegra_smmu *smmu = as->smmu;
|
|
unsigned long offset;
|
|
struct page *page;
|
|
u32 *pte;
|
|
|
|
pte = as_get_pte(as, iova, &page);
|
|
if (!pte)
|
|
return -ENOMEM;
|
|
|
|
*pte = __phys_to_pfn(paddr) | SMMU_PTE_ATTR;
|
|
offset = offset_in_page(pte);
|
|
|
|
smmu->soc->ops->flush_dcache(page, offset, 4);
|
|
smmu_flush_ptc(smmu, page, offset);
|
|
smmu_flush_tlb_group(smmu, as->id, iova);
|
|
smmu_flush(smmu);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static size_t tegra_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
|
|
size_t size)
|
|
{
|
|
struct tegra_smmu_as *as = to_smmu_as(domain);
|
|
struct tegra_smmu *smmu = as->smmu;
|
|
unsigned long offset;
|
|
struct page *page;
|
|
u32 *pte;
|
|
|
|
pte = as_get_pte(as, iova, &page);
|
|
if (!pte)
|
|
return 0;
|
|
|
|
offset = offset_in_page(pte);
|
|
as_put_pte(as, iova);
|
|
|
|
smmu->soc->ops->flush_dcache(page, offset, 4);
|
|
smmu_flush_ptc(smmu, page, offset);
|
|
smmu_flush_tlb_group(smmu, as->id, iova);
|
|
smmu_flush(smmu);
|
|
|
|
return size;
|
|
}
|
|
|
|
static phys_addr_t tegra_smmu_iova_to_phys(struct iommu_domain *domain,
|
|
dma_addr_t iova)
|
|
{
|
|
struct tegra_smmu_as *as = to_smmu_as(domain);
|
|
struct page *page;
|
|
unsigned long pfn;
|
|
u32 *pte;
|
|
|
|
pte = as_get_pte(as, iova, &page);
|
|
pfn = *pte & as->smmu->pfn_mask;
|
|
|
|
return PFN_PHYS(pfn);
|
|
}
|
|
|
|
static struct tegra_smmu *tegra_smmu_find(struct device_node *np)
|
|
{
|
|
struct platform_device *pdev;
|
|
struct tegra_mc *mc;
|
|
|
|
pdev = of_find_device_by_node(np);
|
|
if (!pdev)
|
|
return NULL;
|
|
|
|
mc = platform_get_drvdata(pdev);
|
|
if (!mc)
|
|
return NULL;
|
|
|
|
return mc->smmu;
|
|
}
|
|
|
|
static int tegra_smmu_add_device(struct device *dev)
|
|
{
|
|
struct device_node *np = dev->of_node;
|
|
struct of_phandle_args args;
|
|
unsigned int index = 0;
|
|
|
|
while (of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index,
|
|
&args) == 0) {
|
|
struct tegra_smmu *smmu;
|
|
|
|
smmu = tegra_smmu_find(args.np);
|
|
if (smmu) {
|
|
/*
|
|
* Only a single IOMMU master interface is currently
|
|
* supported by the Linux kernel, so abort after the
|
|
* first match.
|
|
*/
|
|
dev->archdata.iommu = smmu;
|
|
break;
|
|
}
|
|
|
|
index++;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void tegra_smmu_remove_device(struct device *dev)
|
|
{
|
|
dev->archdata.iommu = NULL;
|
|
}
|
|
|
|
static const struct iommu_ops tegra_smmu_ops = {
|
|
.capable = tegra_smmu_capable,
|
|
.domain_alloc = tegra_smmu_domain_alloc,
|
|
.domain_free = tegra_smmu_domain_free,
|
|
.attach_dev = tegra_smmu_attach_dev,
|
|
.detach_dev = tegra_smmu_detach_dev,
|
|
.add_device = tegra_smmu_add_device,
|
|
.remove_device = tegra_smmu_remove_device,
|
|
.map = tegra_smmu_map,
|
|
.unmap = tegra_smmu_unmap,
|
|
.map_sg = default_iommu_map_sg,
|
|
.iova_to_phys = tegra_smmu_iova_to_phys,
|
|
|
|
.pgsize_bitmap = SZ_4K,
|
|
};
|
|
|
|
static void tegra_smmu_ahb_enable(void)
|
|
{
|
|
static const struct of_device_id ahb_match[] = {
|
|
{ .compatible = "nvidia,tegra30-ahb", },
|
|
{ }
|
|
};
|
|
struct device_node *ahb;
|
|
|
|
ahb = of_find_matching_node(NULL, ahb_match);
|
|
if (ahb) {
|
|
tegra_ahb_enable_smmu(ahb);
|
|
of_node_put(ahb);
|
|
}
|
|
}
|
|
|
|
struct tegra_smmu *tegra_smmu_probe(struct device *dev,
|
|
const struct tegra_smmu_soc *soc,
|
|
struct tegra_mc *mc)
|
|
{
|
|
struct tegra_smmu *smmu;
|
|
size_t size;
|
|
u32 value;
|
|
int err;
|
|
|
|
/* This can happen on Tegra20 which doesn't have an SMMU */
|
|
if (!soc)
|
|
return NULL;
|
|
|
|
smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
|
|
if (!smmu)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
/*
|
|
* This is a bit of a hack. Ideally we'd want to simply return this
|
|
* value. However the IOMMU registration process will attempt to add
|
|
* all devices to the IOMMU when bus_set_iommu() is called. In order
|
|
* not to rely on global variables to track the IOMMU instance, we
|
|
* set it here so that it can be looked up from the .add_device()
|
|
* callback via the IOMMU device's .drvdata field.
|
|
*/
|
|
mc->smmu = smmu;
|
|
|
|
size = BITS_TO_LONGS(soc->num_asids) * sizeof(long);
|
|
|
|
smmu->asids = devm_kzalloc(dev, size, GFP_KERNEL);
|
|
if (!smmu->asids)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
mutex_init(&smmu->lock);
|
|
|
|
smmu->regs = mc->regs;
|
|
smmu->soc = soc;
|
|
smmu->dev = dev;
|
|
smmu->mc = mc;
|
|
|
|
smmu->pfn_mask = BIT_MASK(mc->soc->num_address_bits - PAGE_SHIFT) - 1;
|
|
dev_dbg(dev, "address bits: %u, PFN mask: %#lx\n",
|
|
mc->soc->num_address_bits, smmu->pfn_mask);
|
|
|
|
value = SMMU_PTC_CONFIG_ENABLE | SMMU_PTC_CONFIG_INDEX_MAP(0x3f);
|
|
|
|
if (soc->supports_request_limit)
|
|
value |= SMMU_PTC_CONFIG_REQ_LIMIT(8);
|
|
|
|
smmu_writel(smmu, value, SMMU_PTC_CONFIG);
|
|
|
|
value = SMMU_TLB_CONFIG_HIT_UNDER_MISS |
|
|
SMMU_TLB_CONFIG_ACTIVE_LINES(0x20);
|
|
|
|
if (soc->supports_round_robin_arbitration)
|
|
value |= SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION;
|
|
|
|
smmu_writel(smmu, value, SMMU_TLB_CONFIG);
|
|
|
|
smmu_flush_ptc(smmu, NULL, 0);
|
|
smmu_flush_tlb(smmu);
|
|
smmu_writel(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG);
|
|
smmu_flush(smmu);
|
|
|
|
tegra_smmu_ahb_enable();
|
|
|
|
err = bus_set_iommu(&platform_bus_type, &tegra_smmu_ops);
|
|
if (err < 0)
|
|
return ERR_PTR(err);
|
|
|
|
return smmu;
|
|
}
|