474 lines
11 KiB
C
474 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2015 Samsung Electronics Co.Ltd
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* Authors:
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* Hyungwon Hwang <human.hwang@samsung.com>
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*/
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/delay.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_graph.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <video/of_videomode.h>
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#include <video/videomode.h>
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#include <drm/drm_bridge.h>
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#include <drm/drm_encoder.h>
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#include <drm/drm_print.h>
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#include "exynos_drm_drv.h"
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/* Sysreg registers for MIC */
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#define DSD_CFG_MUX 0x1004
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#define MIC0_RGB_MUX (1 << 0)
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#define MIC0_I80_MUX (1 << 1)
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#define MIC0_ON_MUX (1 << 5)
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/* MIC registers */
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#define MIC_OP 0x0
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#define MIC_IP_VER 0x0004
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#define MIC_V_TIMING_0 0x0008
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#define MIC_V_TIMING_1 0x000C
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#define MIC_IMG_SIZE 0x0010
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#define MIC_INPUT_TIMING_0 0x0014
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#define MIC_INPUT_TIMING_1 0x0018
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#define MIC_2D_OUTPUT_TIMING_0 0x001C
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#define MIC_2D_OUTPUT_TIMING_1 0x0020
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#define MIC_2D_OUTPUT_TIMING_2 0x0024
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#define MIC_3D_OUTPUT_TIMING_0 0x0028
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#define MIC_3D_OUTPUT_TIMING_1 0x002C
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#define MIC_3D_OUTPUT_TIMING_2 0x0030
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#define MIC_CORE_PARA_0 0x0034
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#define MIC_CORE_PARA_1 0x0038
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#define MIC_CTC_CTRL 0x0040
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#define MIC_RD_DATA 0x0044
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#define MIC_UPD_REG (1 << 31)
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#define MIC_ON_REG (1 << 30)
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#define MIC_TD_ON_REG (1 << 29)
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#define MIC_BS_CHG_OUT (1 << 16)
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#define MIC_VIDEO_TYPE(x) (((x) & 0xf) << 12)
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#define MIC_PSR_EN (1 << 5)
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#define MIC_SW_RST (1 << 4)
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#define MIC_ALL_RST (1 << 3)
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#define MIC_CORE_VER_CONTROL (1 << 2)
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#define MIC_MODE_SEL_COMMAND_MODE (1 << 1)
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#define MIC_MODE_SEL_MASK (1 << 1)
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#define MIC_CORE_EN (1 << 0)
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#define MIC_V_PULSE_WIDTH(x) (((x) & 0x3fff) << 16)
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#define MIC_V_PERIOD_LINE(x) ((x) & 0x3fff)
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#define MIC_VBP_SIZE(x) (((x) & 0x3fff) << 16)
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#define MIC_VFP_SIZE(x) ((x) & 0x3fff)
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#define MIC_IMG_V_SIZE(x) (((x) & 0x3fff) << 16)
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#define MIC_IMG_H_SIZE(x) ((x) & 0x3fff)
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#define MIC_H_PULSE_WIDTH_IN(x) (((x) & 0x3fff) << 16)
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#define MIC_H_PERIOD_PIXEL_IN(x) ((x) & 0x3fff)
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#define MIC_HBP_SIZE_IN(x) (((x) & 0x3fff) << 16)
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#define MIC_HFP_SIZE_IN(x) ((x) & 0x3fff)
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#define MIC_H_PULSE_WIDTH_2D(x) (((x) & 0x3fff) << 16)
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#define MIC_H_PERIOD_PIXEL_2D(x) ((x) & 0x3fff)
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#define MIC_HBP_SIZE_2D(x) (((x) & 0x3fff) << 16)
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#define MIC_HFP_SIZE_2D(x) ((x) & 0x3fff)
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#define MIC_BS_SIZE_2D(x) ((x) & 0x3fff)
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static char *clk_names[] = { "pclk_mic0", "sclk_rgb_vclk_to_mic0" };
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#define NUM_CLKS ARRAY_SIZE(clk_names)
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static DEFINE_MUTEX(mic_mutex);
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struct exynos_mic {
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struct device *dev;
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void __iomem *reg;
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struct regmap *sysreg;
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struct clk *clks[NUM_CLKS];
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bool i80_mode;
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struct videomode vm;
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struct drm_encoder *encoder;
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struct drm_bridge bridge;
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bool enabled;
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};
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static void mic_set_path(struct exynos_mic *mic, bool enable)
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{
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int ret;
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unsigned int val;
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ret = regmap_read(mic->sysreg, DSD_CFG_MUX, &val);
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if (ret) {
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DRM_DEV_ERROR(mic->dev,
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"mic: Failed to read system register\n");
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return;
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}
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if (enable) {
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if (mic->i80_mode)
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val |= MIC0_I80_MUX;
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else
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val |= MIC0_RGB_MUX;
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val |= MIC0_ON_MUX;
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} else
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val &= ~(MIC0_RGB_MUX | MIC0_I80_MUX | MIC0_ON_MUX);
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ret = regmap_write(mic->sysreg, DSD_CFG_MUX, val);
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if (ret)
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DRM_DEV_ERROR(mic->dev,
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"mic: Failed to read system register\n");
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}
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static int mic_sw_reset(struct exynos_mic *mic)
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{
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unsigned int retry = 100;
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int ret;
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writel(MIC_SW_RST, mic->reg + MIC_OP);
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while (retry-- > 0) {
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ret = readl(mic->reg + MIC_OP);
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if (!(ret & MIC_SW_RST))
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return 0;
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udelay(10);
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}
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return -ETIMEDOUT;
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}
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static void mic_set_porch_timing(struct exynos_mic *mic)
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{
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struct videomode vm = mic->vm;
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u32 reg;
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reg = MIC_V_PULSE_WIDTH(vm.vsync_len) +
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MIC_V_PERIOD_LINE(vm.vsync_len + vm.vactive +
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vm.vback_porch + vm.vfront_porch);
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writel(reg, mic->reg + MIC_V_TIMING_0);
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reg = MIC_VBP_SIZE(vm.vback_porch) +
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MIC_VFP_SIZE(vm.vfront_porch);
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writel(reg, mic->reg + MIC_V_TIMING_1);
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reg = MIC_V_PULSE_WIDTH(vm.hsync_len) +
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MIC_V_PERIOD_LINE(vm.hsync_len + vm.hactive +
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vm.hback_porch + vm.hfront_porch);
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writel(reg, mic->reg + MIC_INPUT_TIMING_0);
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reg = MIC_VBP_SIZE(vm.hback_porch) +
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MIC_VFP_SIZE(vm.hfront_porch);
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writel(reg, mic->reg + MIC_INPUT_TIMING_1);
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}
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static void mic_set_img_size(struct exynos_mic *mic)
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{
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struct videomode *vm = &mic->vm;
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u32 reg;
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reg = MIC_IMG_H_SIZE(vm->hactive) +
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MIC_IMG_V_SIZE(vm->vactive);
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writel(reg, mic->reg + MIC_IMG_SIZE);
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}
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static void mic_set_output_timing(struct exynos_mic *mic)
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{
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struct videomode vm = mic->vm;
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u32 reg, bs_size_2d;
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DRM_DEV_DEBUG(mic->dev, "w: %u, h: %u\n", vm.hactive, vm.vactive);
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bs_size_2d = ((vm.hactive >> 2) << 1) + (vm.vactive % 4);
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reg = MIC_BS_SIZE_2D(bs_size_2d);
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writel(reg, mic->reg + MIC_2D_OUTPUT_TIMING_2);
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if (!mic->i80_mode) {
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reg = MIC_H_PULSE_WIDTH_2D(vm.hsync_len) +
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MIC_H_PERIOD_PIXEL_2D(vm.hsync_len + bs_size_2d +
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vm.hback_porch + vm.hfront_porch);
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writel(reg, mic->reg + MIC_2D_OUTPUT_TIMING_0);
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reg = MIC_HBP_SIZE_2D(vm.hback_porch) +
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MIC_H_PERIOD_PIXEL_2D(vm.hfront_porch);
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writel(reg, mic->reg + MIC_2D_OUTPUT_TIMING_1);
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}
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}
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static void mic_set_reg_on(struct exynos_mic *mic, bool enable)
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{
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u32 reg = readl(mic->reg + MIC_OP);
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if (enable) {
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reg &= ~(MIC_MODE_SEL_MASK | MIC_CORE_VER_CONTROL | MIC_PSR_EN);
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reg |= (MIC_CORE_EN | MIC_BS_CHG_OUT | MIC_ON_REG);
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reg &= ~MIC_MODE_SEL_COMMAND_MODE;
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if (mic->i80_mode)
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reg |= MIC_MODE_SEL_COMMAND_MODE;
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} else {
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reg &= ~MIC_CORE_EN;
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}
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reg |= MIC_UPD_REG;
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writel(reg, mic->reg + MIC_OP);
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}
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static void mic_disable(struct drm_bridge *bridge) { }
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static void mic_post_disable(struct drm_bridge *bridge)
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{
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struct exynos_mic *mic = bridge->driver_private;
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mutex_lock(&mic_mutex);
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if (!mic->enabled)
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goto already_disabled;
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mic_set_path(mic, 0);
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pm_runtime_put(mic->dev);
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mic->enabled = 0;
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already_disabled:
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mutex_unlock(&mic_mutex);
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}
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static void mic_mode_set(struct drm_bridge *bridge,
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const struct drm_display_mode *mode,
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const struct drm_display_mode *adjusted_mode)
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{
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struct exynos_mic *mic = bridge->driver_private;
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mutex_lock(&mic_mutex);
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drm_display_mode_to_videomode(mode, &mic->vm);
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mic->i80_mode = to_exynos_crtc(bridge->encoder->crtc)->i80_mode;
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mutex_unlock(&mic_mutex);
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}
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static void mic_pre_enable(struct drm_bridge *bridge)
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{
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struct exynos_mic *mic = bridge->driver_private;
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int ret;
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mutex_lock(&mic_mutex);
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if (mic->enabled)
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goto unlock;
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ret = pm_runtime_get_sync(mic->dev);
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if (ret < 0)
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goto unlock;
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mic_set_path(mic, 1);
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ret = mic_sw_reset(mic);
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if (ret) {
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DRM_DEV_ERROR(mic->dev, "Failed to reset\n");
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goto turn_off;
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}
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if (!mic->i80_mode)
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mic_set_porch_timing(mic);
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mic_set_img_size(mic);
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mic_set_output_timing(mic);
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mic_set_reg_on(mic, 1);
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mic->enabled = 1;
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mutex_unlock(&mic_mutex);
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return;
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turn_off:
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pm_runtime_put(mic->dev);
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unlock:
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mutex_unlock(&mic_mutex);
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}
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static void mic_enable(struct drm_bridge *bridge) { }
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static const struct drm_bridge_funcs mic_bridge_funcs = {
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.disable = mic_disable,
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.post_disable = mic_post_disable,
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.mode_set = mic_mode_set,
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.pre_enable = mic_pre_enable,
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.enable = mic_enable,
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};
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static int exynos_mic_bind(struct device *dev, struct device *master,
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void *data)
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{
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struct exynos_mic *mic = dev_get_drvdata(dev);
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mic->bridge.driver_private = mic;
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return 0;
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}
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static void exynos_mic_unbind(struct device *dev, struct device *master,
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void *data)
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{
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struct exynos_mic *mic = dev_get_drvdata(dev);
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mutex_lock(&mic_mutex);
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if (!mic->enabled)
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goto already_disabled;
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pm_runtime_put(mic->dev);
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already_disabled:
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mutex_unlock(&mic_mutex);
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}
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static const struct component_ops exynos_mic_component_ops = {
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.bind = exynos_mic_bind,
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.unbind = exynos_mic_unbind,
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};
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#ifdef CONFIG_PM
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static int exynos_mic_suspend(struct device *dev)
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{
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struct exynos_mic *mic = dev_get_drvdata(dev);
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int i;
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for (i = NUM_CLKS - 1; i > -1; i--)
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clk_disable_unprepare(mic->clks[i]);
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return 0;
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}
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static int exynos_mic_resume(struct device *dev)
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{
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struct exynos_mic *mic = dev_get_drvdata(dev);
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int ret, i;
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for (i = 0; i < NUM_CLKS; i++) {
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ret = clk_prepare_enable(mic->clks[i]);
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if (ret < 0) {
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DRM_DEV_ERROR(dev, "Failed to enable clock (%s)\n",
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clk_names[i]);
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while (--i > -1)
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clk_disable_unprepare(mic->clks[i]);
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return ret;
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}
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}
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return 0;
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}
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#endif
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static const struct dev_pm_ops exynos_mic_pm_ops = {
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SET_RUNTIME_PM_OPS(exynos_mic_suspend, exynos_mic_resume, NULL)
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SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
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pm_runtime_force_resume)
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};
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static int exynos_mic_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct exynos_mic *mic;
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struct resource res;
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int ret, i;
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mic = devm_kzalloc(dev, sizeof(*mic), GFP_KERNEL);
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if (!mic) {
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DRM_DEV_ERROR(dev,
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"mic: Failed to allocate memory for MIC object\n");
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ret = -ENOMEM;
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goto err;
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}
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mic->dev = dev;
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ret = of_address_to_resource(dev->of_node, 0, &res);
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if (ret) {
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DRM_DEV_ERROR(dev, "mic: Failed to get mem region for MIC\n");
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goto err;
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}
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mic->reg = devm_ioremap(dev, res.start, resource_size(&res));
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if (!mic->reg) {
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DRM_DEV_ERROR(dev, "mic: Failed to remap for MIC\n");
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ret = -ENOMEM;
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goto err;
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}
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mic->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
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"samsung,disp-syscon");
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if (IS_ERR(mic->sysreg)) {
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DRM_DEV_ERROR(dev, "mic: Failed to get system register.\n");
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ret = PTR_ERR(mic->sysreg);
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goto err;
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}
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for (i = 0; i < NUM_CLKS; i++) {
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mic->clks[i] = devm_clk_get(dev, clk_names[i]);
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if (IS_ERR(mic->clks[i])) {
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DRM_DEV_ERROR(dev, "mic: Failed to get clock (%s)\n",
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clk_names[i]);
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ret = PTR_ERR(mic->clks[i]);
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goto err;
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}
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}
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platform_set_drvdata(pdev, mic);
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mic->bridge.funcs = &mic_bridge_funcs;
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mic->bridge.of_node = dev->of_node;
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drm_bridge_add(&mic->bridge);
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pm_runtime_enable(dev);
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ret = component_add(dev, &exynos_mic_component_ops);
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if (ret)
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goto err_pm;
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DRM_DEV_DEBUG_KMS(dev, "MIC has been probed\n");
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return 0;
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err_pm:
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pm_runtime_disable(dev);
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err:
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return ret;
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}
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static int exynos_mic_remove(struct platform_device *pdev)
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{
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struct exynos_mic *mic = platform_get_drvdata(pdev);
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component_del(&pdev->dev, &exynos_mic_component_ops);
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pm_runtime_disable(&pdev->dev);
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drm_bridge_remove(&mic->bridge);
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return 0;
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}
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static const struct of_device_id exynos_mic_of_match[] = {
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{ .compatible = "samsung,exynos5433-mic" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, exynos_mic_of_match);
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struct platform_driver mic_driver = {
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.probe = exynos_mic_probe,
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.remove = exynos_mic_remove,
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.driver = {
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.name = "exynos-mic",
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.pm = &exynos_mic_pm_ops,
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.owner = THIS_MODULE,
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.of_match_table = exynos_mic_of_match,
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},
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};
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