467 lines
9.9 KiB
C
467 lines
9.9 KiB
C
/*
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* linux/arch/arm/mach-pxa/generic.c
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*
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* Author: Nicolas Pitre
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* Created: Jun 15, 2001
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* Copyright: MontaVista Software Inc.
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*
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* Code common to all PXA machines.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Since this file should be linked before any other machine specific file,
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* the __initcall() here will be executed first. This serves as default
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* initialization stuff for PXA machines which can be overridden later if
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* need be.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/platform_device.h>
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#include <linux/ioport.h>
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#include <linux/pm.h>
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#include <linux/string.h>
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#include <linux/sched.h>
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#include <asm/cnt32_to_63.h>
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#include <asm/div64.h>
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#include <asm/hardware.h>
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#include <asm/irq.h>
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#include <asm/system.h>
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#include <asm/pgtable.h>
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#include <asm/mach/map.h>
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#include <asm/arch/pxa-regs.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/udc.h>
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#include <asm/arch/pxafb.h>
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#include <asm/arch/mmc.h>
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#include <asm/arch/irda.h>
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#include <asm/arch/i2c.h>
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#include "generic.h"
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/*
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* This is the PXA2xx sched_clock implementation. This has a resolution
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* of at least 308ns and a maximum value that depends on the value of
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* CLOCK_TICK_RATE.
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*
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* The return value is guaranteed to be monotonic in that range as
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* long as there is always less than 582 seconds between successive
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* calls to this function.
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*/
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unsigned long long sched_clock(void)
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{
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unsigned long long v = cnt32_to_63(OSCR);
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/* Note: top bit ov v needs cleared unless multiplier is even. */
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#if CLOCK_TICK_RATE == 3686400
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/* 1E9 / 3686400 => 78125 / 288, max value = 32025597s (370 days). */
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/* The <<1 is used to get rid of tick.hi top bit */
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v *= 78125<<1;
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do_div(v, 288<<1);
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#elif CLOCK_TICK_RATE == 3250000
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/* 1E9 / 3250000 => 4000 / 13, max value = 709490156s (8211 days) */
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v *= 4000;
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do_div(v, 13);
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#elif CLOCK_TICK_RATE == 3249600
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/* 1E9 / 3249600 => 625000 / 2031, max value = 4541295s (52 days) */
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v *= 625000;
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do_div(v, 2031);
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#else
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#warning "consider fixing sched_clock for your value of CLOCK_TICK_RATE"
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/*
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* 96-bit math to perform tick * NSEC_PER_SEC / CLOCK_TICK_RATE for
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* any value of CLOCK_TICK_RATE. Max value is in the 80 thousand
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* years range and truncation to unsigned long long limits it to
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* sched_clock's max range of ~584 years. This is nice but with
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* higher computation cost.
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*/
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{
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union {
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unsigned long long val;
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struct { unsigned long lo, hi; };
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} x;
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unsigned long long y;
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x.val = v;
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x.hi &= 0x7fffffff;
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y = (unsigned long long)x.lo * NSEC_PER_SEC;
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x.lo = y;
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y = (y >> 32) + (unsigned long long)x.hi * NSEC_PER_SEC;
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x.hi = do_div(y, CLOCK_TICK_RATE);
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do_div(x.val, CLOCK_TICK_RATE);
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x.hi += y;
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v = x.val;
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}
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#endif
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return v;
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}
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/*
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* Handy function to set GPIO alternate functions
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*/
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int pxa_gpio_mode(int gpio_mode)
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{
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unsigned long flags;
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int gpio = gpio_mode & GPIO_MD_MASK_NR;
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int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
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int gafr;
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if (gpio > PXA_LAST_GPIO)
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return -EINVAL;
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local_irq_save(flags);
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if (gpio_mode & GPIO_DFLT_LOW)
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GPCR(gpio) = GPIO_bit(gpio);
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else if (gpio_mode & GPIO_DFLT_HIGH)
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GPSR(gpio) = GPIO_bit(gpio);
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if (gpio_mode & GPIO_MD_MASK_DIR)
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GPDR(gpio) |= GPIO_bit(gpio);
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else
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GPDR(gpio) &= ~GPIO_bit(gpio);
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gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
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GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2));
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local_irq_restore(flags);
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return 0;
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}
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EXPORT_SYMBOL(pxa_gpio_mode);
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/*
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* Return GPIO level
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*/
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int pxa_gpio_get_value(unsigned gpio)
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{
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return __gpio_get_value(gpio);
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}
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EXPORT_SYMBOL(pxa_gpio_get_value);
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/*
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* Set output GPIO level
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*/
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void pxa_gpio_set_value(unsigned gpio, int value)
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{
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__gpio_set_value(gpio, value);
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}
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EXPORT_SYMBOL(pxa_gpio_set_value);
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/*
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* Routine to safely enable or disable a clock in the CKEN
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*/
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void pxa_set_cken(int clock, int enable)
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{
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unsigned long flags;
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local_irq_save(flags);
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if (enable)
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CKEN |= (1 << clock);
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else
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CKEN &= ~(1 << clock);
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local_irq_restore(flags);
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}
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EXPORT_SYMBOL(pxa_set_cken);
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/*
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* Intel PXA2xx internal register mapping.
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*
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* Note 1: not all PXA2xx variants implement all those addresses.
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*
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* Note 2: virtual 0xfffe0000-0xffffffff is reserved for the vector table
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* and cache flush area.
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*/
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static struct map_desc standard_io_desc[] __initdata = {
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{ /* Devs */
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.virtual = 0xf2000000,
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.pfn = __phys_to_pfn(0x40000000),
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.length = 0x02000000,
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.type = MT_DEVICE
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}, { /* LCD */
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.virtual = 0xf4000000,
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.pfn = __phys_to_pfn(0x44000000),
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.length = 0x00100000,
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.type = MT_DEVICE
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}, { /* Mem Ctl */
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.virtual = 0xf6000000,
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.pfn = __phys_to_pfn(0x48000000),
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.length = 0x00100000,
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.type = MT_DEVICE
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}, { /* USB host */
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.virtual = 0xf8000000,
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.pfn = __phys_to_pfn(0x4c000000),
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.length = 0x00100000,
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.type = MT_DEVICE
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}, { /* Camera */
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.virtual = 0xfa000000,
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.pfn = __phys_to_pfn(0x50000000),
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.length = 0x00100000,
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.type = MT_DEVICE
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}, { /* IMem ctl */
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.virtual = 0xfe000000,
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.pfn = __phys_to_pfn(0x58000000),
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.length = 0x00100000,
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.type = MT_DEVICE
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}, { /* UNCACHED_PHYS_0 */
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.virtual = 0xff000000,
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.pfn = __phys_to_pfn(0x00000000),
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.length = 0x00100000,
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.type = MT_DEVICE
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}
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};
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void __init pxa_map_io(void)
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{
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iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
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get_clk_frequency_khz(1);
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}
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static struct resource pxamci_resources[] = {
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[0] = {
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.start = 0x41100000,
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.end = 0x41100fff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_MMC,
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.end = IRQ_MMC,
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.flags = IORESOURCE_IRQ,
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},
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};
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static u64 pxamci_dmamask = 0xffffffffUL;
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static struct platform_device pxamci_device = {
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.name = "pxa2xx-mci",
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.id = -1,
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.dev = {
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.dma_mask = &pxamci_dmamask,
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.coherent_dma_mask = 0xffffffff,
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},
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.num_resources = ARRAY_SIZE(pxamci_resources),
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.resource = pxamci_resources,
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};
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void __init pxa_set_mci_info(struct pxamci_platform_data *info)
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{
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pxamci_device.dev.platform_data = info;
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}
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static struct pxa2xx_udc_mach_info pxa_udc_info;
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void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
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{
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memcpy(&pxa_udc_info, info, sizeof *info);
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}
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static struct resource pxa2xx_udc_resources[] = {
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[0] = {
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.start = 0x40600000,
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.end = 0x4060ffff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_USB,
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.end = IRQ_USB,
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.flags = IORESOURCE_IRQ,
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},
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};
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static u64 udc_dma_mask = ~(u32)0;
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static struct platform_device udc_device = {
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.name = "pxa2xx-udc",
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.id = -1,
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.resource = pxa2xx_udc_resources,
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.num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
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.dev = {
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.platform_data = &pxa_udc_info,
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.dma_mask = &udc_dma_mask,
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}
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};
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static struct resource pxafb_resources[] = {
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[0] = {
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.start = 0x44000000,
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.end = 0x4400ffff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_LCD,
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.end = IRQ_LCD,
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.flags = IORESOURCE_IRQ,
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},
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};
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static u64 fb_dma_mask = ~(u64)0;
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static struct platform_device pxafb_device = {
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.name = "pxa2xx-fb",
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.id = -1,
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.dev = {
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.dma_mask = &fb_dma_mask,
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.coherent_dma_mask = 0xffffffff,
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},
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.num_resources = ARRAY_SIZE(pxafb_resources),
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.resource = pxafb_resources,
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};
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void __init set_pxa_fb_info(struct pxafb_mach_info *info)
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{
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pxafb_device.dev.platform_data = info;
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}
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void __init set_pxa_fb_parent(struct device *parent_dev)
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{
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pxafb_device.dev.parent = parent_dev;
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}
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static struct platform_device ffuart_device = {
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.name = "pxa2xx-uart",
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.id = 0,
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};
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static struct platform_device btuart_device = {
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.name = "pxa2xx-uart",
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.id = 1,
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};
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static struct platform_device stuart_device = {
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.name = "pxa2xx-uart",
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.id = 2,
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};
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static struct platform_device hwuart_device = {
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.name = "pxa2xx-uart",
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.id = 3,
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};
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static struct resource i2c_resources[] = {
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{
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.start = 0x40301680,
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.end = 0x403016a3,
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.flags = IORESOURCE_MEM,
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}, {
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.start = IRQ_I2C,
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.end = IRQ_I2C,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device i2c_device = {
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.name = "pxa2xx-i2c",
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.id = 0,
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.resource = i2c_resources,
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.num_resources = ARRAY_SIZE(i2c_resources),
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};
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#ifdef CONFIG_PXA27x
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static struct resource i2c_power_resources[] = {
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{
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.start = 0x40f00180,
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.end = 0x40f001a3,
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.flags = IORESOURCE_MEM,
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}, {
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.start = IRQ_PWRI2C,
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.end = IRQ_PWRI2C,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device i2c_power_device = {
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.name = "pxa2xx-i2c",
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.id = 1,
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.resource = i2c_power_resources,
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.num_resources = ARRAY_SIZE(i2c_resources),
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};
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#endif
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void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
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{
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i2c_device.dev.platform_data = info;
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}
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static struct resource i2s_resources[] = {
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{
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.start = 0x40400000,
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.end = 0x40400083,
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.flags = IORESOURCE_MEM,
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}, {
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.start = IRQ_I2S,
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.end = IRQ_I2S,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device i2s_device = {
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.name = "pxa2xx-i2s",
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.id = -1,
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.resource = i2s_resources,
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.num_resources = ARRAY_SIZE(i2s_resources),
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};
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static u64 pxaficp_dmamask = ~(u32)0;
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static struct platform_device pxaficp_device = {
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.name = "pxa2xx-ir",
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.id = -1,
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.dev = {
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.dma_mask = &pxaficp_dmamask,
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.coherent_dma_mask = 0xffffffff,
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},
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};
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void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
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{
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pxaficp_device.dev.platform_data = info;
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}
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static struct platform_device pxartc_device = {
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.name = "sa1100-rtc",
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.id = -1,
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};
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static struct platform_device *devices[] __initdata = {
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&pxamci_device,
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&udc_device,
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&pxafb_device,
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&ffuart_device,
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&btuart_device,
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&stuart_device,
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&pxaficp_device,
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&i2c_device,
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#ifdef CONFIG_PXA27x
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&i2c_power_device,
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#endif
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&i2s_device,
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&pxartc_device,
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};
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static int __init pxa_init(void)
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{
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int cpuid, ret;
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ret = platform_add_devices(devices, ARRAY_SIZE(devices));
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if (ret)
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return ret;
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/* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
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cpuid = read_cpuid(CPUID_ID);
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if (((cpuid >> 4) & 0xfff) == 0x2d0 ||
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((cpuid >> 4) & 0xfff) == 0x290)
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ret = platform_device_register(&hwuart_device);
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return ret;
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}
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subsys_initcall(pxa_init);
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