99 lines
3.4 KiB
Plaintext
99 lines
3.4 KiB
Plaintext
CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
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Flash chips (Memory Technology Devices) are often used for solid state
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file systems on embedded devices.
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- compatible : should contain the specific model of mtd chip(s)
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used, if known, followed by either "cfi-flash", "jedec-flash",
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"mtd-ram" or "mtd-rom".
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- reg : Address range(s) of the mtd chip(s)
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It's possible to (optionally) define multiple "reg" tuples so that
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non-identical chips can be described in one node.
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- bank-width : Width (in bytes) of the bank. Equal to the
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device width times the number of interleaved chips.
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- device-width : (optional) Width of a single mtd chip. If
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omitted, assumed to be equal to 'bank-width'.
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- #address-cells, #size-cells : Must be present if the device has
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sub-nodes representing partitions (see below). In this case
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both #address-cells and #size-cells must be equal to 1.
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- no-unaligned-direct-access: boolean to disable the default direct
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mapping of the flash.
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On some platforms (e.g. MPC5200) a direct 1:1 mapping may cause
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problems with JFFS2 usage, as the local bus (LPB) doesn't support
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unaligned accesses as implemented in the JFFS2 code via memcpy().
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By defining "no-unaligned-direct-access", the flash will not be
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exposed directly to the MTD users (e.g. JFFS2) any more.
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- linux,mtd-name: allow to specify the mtd name for retro capability with
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physmap-flash drivers as boot loader pass the mtd partition via the old
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device name physmap-flash.
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- use-advanced-sector-protection: boolean to enable support for the
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advanced sector protection (Spansion: PPB - Persistent Protection
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Bits) locking.
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- addr-gpios : (optional) List of GPIO descriptors that will be used to
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address the MSBs address lines. The order goes from LSB to MSB.
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For JEDEC compatible devices, the following additional properties
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are defined:
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- vendor-id : Contains the flash chip's vendor id (1 byte).
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- device-id : Contains the flash chip's device id (1 byte).
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For ROM compatible devices (and ROM fallback from cfi-flash), the following
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additional (optional) property is defined:
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- erase-size : The chip's physical erase block size in bytes.
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The device tree may optionally contain endianness property.
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little-endian or big-endian : It Represents the endianness that should be used
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by the controller to properly read/write data
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from/to the flash. If this property is missing,
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the endianness is chosen by the system
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(potentially based on extra configuration options).
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The device tree may optionally contain sub-nodes describing partitions of the
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address space. See partition.txt for more detail.
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Example:
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flash@ff000000 {
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compatible = "amd,am29lv128ml", "cfi-flash";
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reg = <ff000000 01000000>;
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bank-width = <4>;
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device-width = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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fs@0 {
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label = "fs";
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reg = <0 f80000>;
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};
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firmware@f80000 {
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label ="firmware";
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reg = <f80000 80000>;
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read-only;
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};
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};
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Here an example with multiple "reg" tuples:
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flash@f0000000,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "intel,PC48F4400P0VB", "cfi-flash";
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reg = <0 0x00000000 0x02000000
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0 0x02000000 0x02000000>;
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bank-width = <2>;
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partition@0 {
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label = "test-part1";
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reg = <0 0x04000000>;
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};
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};
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An example using SRAM:
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sram@2,0 {
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compatible = "samsung,k6f1616u6a", "mtd-ram";
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reg = <2 0 0x00200000>;
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bank-width = <2>;
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};
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