407 lines
11 KiB
C
407 lines
11 KiB
C
/*
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* Copyright 2012 Michael Ellerman, IBM Corporation.
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* Copyright 2012 Benjamin Herrenschmidt, IBM Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/kvm_host.h>
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#include <linux/err.h>
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#include <asm/kvm_book3s.h>
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#include <asm/kvm_ppc.h>
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#include <asm/hvcall.h>
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#include <asm/xics.h>
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#include <asm/debug.h>
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#include <asm/synch.h>
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#include <asm/ppc-opcode.h>
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#include "book3s_xics.h"
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#define DEBUG_PASSUP
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static inline void rm_writeb(unsigned long paddr, u8 val)
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{
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__asm__ __volatile__("sync; stbcix %0,0,%1"
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: : "r" (val), "r" (paddr) : "memory");
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}
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static void icp_rm_set_vcpu_irq(struct kvm_vcpu *vcpu,
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struct kvm_vcpu *this_vcpu)
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{
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struct kvmppc_icp *this_icp = this_vcpu->arch.icp;
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unsigned long xics_phys;
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int cpu;
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/* Mark the target VCPU as having an interrupt pending */
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vcpu->stat.queue_intr++;
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set_bit(BOOK3S_IRQPRIO_EXTERNAL_LEVEL, &vcpu->arch.pending_exceptions);
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/* Kick self ? Just set MER and return */
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if (vcpu == this_vcpu) {
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mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) | LPCR_MER);
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return;
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}
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/* Check if the core is loaded, if not, too hard */
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cpu = vcpu->cpu;
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if (cpu < 0 || cpu >= nr_cpu_ids) {
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this_icp->rm_action |= XICS_RM_KICK_VCPU;
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this_icp->rm_kick_target = vcpu;
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return;
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}
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/* In SMT cpu will always point to thread 0, we adjust it */
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cpu += vcpu->arch.ptid;
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/* Not too hard, then poke the target */
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xics_phys = paca[cpu].kvm_hstate.xics_phys;
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rm_writeb(xics_phys + XICS_MFRR, IPI_PRIORITY);
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}
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static void icp_rm_clr_vcpu_irq(struct kvm_vcpu *vcpu)
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{
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/* Note: Only called on self ! */
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clear_bit(BOOK3S_IRQPRIO_EXTERNAL_LEVEL,
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&vcpu->arch.pending_exceptions);
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mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) & ~LPCR_MER);
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}
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static inline bool icp_rm_try_update(struct kvmppc_icp *icp,
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union kvmppc_icp_state old,
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union kvmppc_icp_state new)
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{
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struct kvm_vcpu *this_vcpu = local_paca->kvm_hstate.kvm_vcpu;
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bool success;
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/* Calculate new output value */
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new.out_ee = (new.xisr && (new.pending_pri < new.cppr));
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/* Attempt atomic update */
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success = cmpxchg64(&icp->state.raw, old.raw, new.raw) == old.raw;
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if (!success)
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goto bail;
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/*
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* Check for output state update
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*
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* Note that this is racy since another processor could be updating
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* the state already. This is why we never clear the interrupt output
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* here, we only ever set it. The clear only happens prior to doing
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* an update and only by the processor itself. Currently we do it
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* in Accept (H_XIRR) and Up_Cppr (H_XPPR).
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*
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* We also do not try to figure out whether the EE state has changed,
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* we unconditionally set it if the new state calls for it. The reason
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* for that is that we opportunistically remove the pending interrupt
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* flag when raising CPPR, so we need to set it back here if an
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* interrupt is still pending.
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*/
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if (new.out_ee)
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icp_rm_set_vcpu_irq(icp->vcpu, this_vcpu);
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/* Expose the state change for debug purposes */
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this_vcpu->arch.icp->rm_dbgstate = new;
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this_vcpu->arch.icp->rm_dbgtgt = icp->vcpu;
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bail:
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return success;
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}
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static inline int check_too_hard(struct kvmppc_xics *xics,
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struct kvmppc_icp *icp)
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{
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return (xics->real_mode_dbg || icp->rm_action) ? H_TOO_HARD : H_SUCCESS;
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}
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static void icp_rm_down_cppr(struct kvmppc_xics *xics, struct kvmppc_icp *icp,
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u8 new_cppr)
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{
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union kvmppc_icp_state old_state, new_state;
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bool resend;
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/*
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* This handles several related states in one operation:
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*
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* ICP State: Down_CPPR
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*
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* Load CPPR with new value and if the XISR is 0
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* then check for resends:
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*
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* ICP State: Resend
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*
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* If MFRR is more favored than CPPR, check for IPIs
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* and notify ICS of a potential resend. This is done
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* asynchronously (when used in real mode, we will have
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* to exit here).
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*
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* We do not handle the complete Check_IPI as documented
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* here. In the PAPR, this state will be used for both
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* Set_MFRR and Down_CPPR. However, we know that we aren't
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* changing the MFRR state here so we don't need to handle
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* the case of an MFRR causing a reject of a pending irq,
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* this will have been handled when the MFRR was set in the
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* first place.
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*
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* Thus we don't have to handle rejects, only resends.
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*
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* When implementing real mode for HV KVM, resend will lead to
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* a H_TOO_HARD return and the whole transaction will be handled
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* in virtual mode.
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*/
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do {
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old_state = new_state = ACCESS_ONCE(icp->state);
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/* Down_CPPR */
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new_state.cppr = new_cppr;
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/*
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* Cut down Resend / Check_IPI / IPI
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*
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* The logic is that we cannot have a pending interrupt
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* trumped by an IPI at this point (see above), so we
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* know that either the pending interrupt is already an
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* IPI (in which case we don't care to override it) or
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* it's either more favored than us or non existent
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*/
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if (new_state.mfrr < new_cppr &&
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new_state.mfrr <= new_state.pending_pri) {
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new_state.pending_pri = new_state.mfrr;
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new_state.xisr = XICS_IPI;
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}
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/* Latch/clear resend bit */
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resend = new_state.need_resend;
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new_state.need_resend = 0;
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} while (!icp_rm_try_update(icp, old_state, new_state));
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/*
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* Now handle resend checks. Those are asynchronous to the ICP
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* state update in HW (ie bus transactions) so we can handle them
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* separately here as well.
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*/
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if (resend)
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icp->rm_action |= XICS_RM_CHECK_RESEND;
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}
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unsigned long kvmppc_rm_h_xirr(struct kvm_vcpu *vcpu)
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{
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union kvmppc_icp_state old_state, new_state;
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struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
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struct kvmppc_icp *icp = vcpu->arch.icp;
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u32 xirr;
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if (!xics || !xics->real_mode)
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return H_TOO_HARD;
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/* First clear the interrupt */
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icp_rm_clr_vcpu_irq(icp->vcpu);
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/*
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* ICP State: Accept_Interrupt
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*
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* Return the pending interrupt (if any) along with the
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* current CPPR, then clear the XISR & set CPPR to the
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* pending priority
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*/
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do {
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old_state = new_state = ACCESS_ONCE(icp->state);
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xirr = old_state.xisr | (((u32)old_state.cppr) << 24);
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if (!old_state.xisr)
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break;
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new_state.cppr = new_state.pending_pri;
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new_state.pending_pri = 0xff;
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new_state.xisr = 0;
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} while (!icp_rm_try_update(icp, old_state, new_state));
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/* Return the result in GPR4 */
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vcpu->arch.gpr[4] = xirr;
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return check_too_hard(xics, icp);
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}
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int kvmppc_rm_h_ipi(struct kvm_vcpu *vcpu, unsigned long server,
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unsigned long mfrr)
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{
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union kvmppc_icp_state old_state, new_state;
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struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
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struct kvmppc_icp *icp, *this_icp = vcpu->arch.icp;
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u32 reject;
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bool resend;
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bool local;
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if (!xics || !xics->real_mode)
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return H_TOO_HARD;
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local = this_icp->server_num == server;
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if (local)
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icp = this_icp;
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else
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icp = kvmppc_xics_find_server(vcpu->kvm, server);
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if (!icp)
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return H_PARAMETER;
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/*
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* ICP state: Set_MFRR
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*
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* If the CPPR is more favored than the new MFRR, then
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* nothing needs to be done as there can be no XISR to
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* reject.
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*
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* If the CPPR is less favored, then we might be replacing
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* an interrupt, and thus need to possibly reject it as in
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*
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* ICP state: Check_IPI
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*/
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do {
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old_state = new_state = ACCESS_ONCE(icp->state);
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/* Set_MFRR */
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new_state.mfrr = mfrr;
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/* Check_IPI */
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reject = 0;
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resend = false;
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if (mfrr < new_state.cppr) {
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/* Reject a pending interrupt if not an IPI */
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if (mfrr <= new_state.pending_pri)
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reject = new_state.xisr;
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new_state.pending_pri = mfrr;
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new_state.xisr = XICS_IPI;
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}
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if (mfrr > old_state.mfrr && mfrr > new_state.cppr) {
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resend = new_state.need_resend;
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new_state.need_resend = 0;
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}
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} while (!icp_rm_try_update(icp, old_state, new_state));
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/* Pass rejects to virtual mode */
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if (reject && reject != XICS_IPI) {
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this_icp->rm_action |= XICS_RM_REJECT;
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this_icp->rm_reject = reject;
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}
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/* Pass resends to virtual mode */
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if (resend)
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this_icp->rm_action |= XICS_RM_CHECK_RESEND;
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return check_too_hard(xics, this_icp);
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}
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int kvmppc_rm_h_cppr(struct kvm_vcpu *vcpu, unsigned long cppr)
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{
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union kvmppc_icp_state old_state, new_state;
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struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
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struct kvmppc_icp *icp = vcpu->arch.icp;
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u32 reject;
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if (!xics || !xics->real_mode)
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return H_TOO_HARD;
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/*
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* ICP State: Set_CPPR
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*
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* We can safely compare the new value with the current
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* value outside of the transaction as the CPPR is only
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* ever changed by the processor on itself
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*/
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if (cppr > icp->state.cppr) {
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icp_rm_down_cppr(xics, icp, cppr);
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goto bail;
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} else if (cppr == icp->state.cppr)
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return H_SUCCESS;
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/*
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* ICP State: Up_CPPR
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*
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* The processor is raising its priority, this can result
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* in a rejection of a pending interrupt:
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*
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* ICP State: Reject_Current
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*
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* We can remove EE from the current processor, the update
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* transaction will set it again if needed
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*/
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icp_rm_clr_vcpu_irq(icp->vcpu);
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do {
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old_state = new_state = ACCESS_ONCE(icp->state);
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reject = 0;
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new_state.cppr = cppr;
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if (cppr <= new_state.pending_pri) {
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reject = new_state.xisr;
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new_state.xisr = 0;
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new_state.pending_pri = 0xff;
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}
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} while (!icp_rm_try_update(icp, old_state, new_state));
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/* Pass rejects to virtual mode */
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if (reject && reject != XICS_IPI) {
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icp->rm_action |= XICS_RM_REJECT;
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icp->rm_reject = reject;
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}
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bail:
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return check_too_hard(xics, icp);
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}
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int kvmppc_rm_h_eoi(struct kvm_vcpu *vcpu, unsigned long xirr)
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{
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struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
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struct kvmppc_icp *icp = vcpu->arch.icp;
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struct kvmppc_ics *ics;
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struct ics_irq_state *state;
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u32 irq = xirr & 0x00ffffff;
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u16 src;
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if (!xics || !xics->real_mode)
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return H_TOO_HARD;
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/*
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* ICP State: EOI
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*
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* Note: If EOI is incorrectly used by SW to lower the CPPR
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* value (ie more favored), we do not check for rejection of
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* a pending interrupt, this is a SW error and PAPR sepcifies
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* that we don't have to deal with it.
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*
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* The sending of an EOI to the ICS is handled after the
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* CPPR update
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*
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* ICP State: Down_CPPR which we handle
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* in a separate function as it's shared with H_CPPR.
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*/
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icp_rm_down_cppr(xics, icp, xirr >> 24);
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/* IPIs have no EOI */
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if (irq == XICS_IPI)
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goto bail;
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/*
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* EOI handling: If the interrupt is still asserted, we need to
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* resend it. We can take a lockless "peek" at the ICS state here.
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*
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* "Message" interrupts will never have "asserted" set
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*/
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ics = kvmppc_xics_find_ics(xics, irq, &src);
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if (!ics)
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goto bail;
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state = &ics->irq_state[src];
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/* Still asserted, resend it, we make it look like a reject */
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if (state->asserted) {
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icp->rm_action |= XICS_RM_REJECT;
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icp->rm_reject = irq;
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}
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bail:
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return check_too_hard(xics, icp);
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}
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