76 lines
2.2 KiB
Plaintext
76 lines
2.2 KiB
Plaintext
S3C24XX CPUfreq support
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=======================
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Introduction
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------------
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The S3C24XX series support a number of power saving systems, such as
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the ability to change the core, memory and peripheral operating
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frequencies. The core control is exported via the CPUFreq driver
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which has a number of different manual or automatic controls over the
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rate the core is running at.
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There are two forms of the driver depending on the specific CPU and
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how the clocks are arranged. The first implementation used as single
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PLL to feed the ARM, memory and peripherals via a series of dividers
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and muxes and this is the implementation that is documented here. A
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newer version where there is a separate PLL and clock divider for the
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ARM core is available as a separate driver.
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Layout
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------
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The code core manages the CPU specific drivers, any data that they
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need to register and the interface to the generic drivers/cpufreq
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system. Each CPU registers a driver to control the PLL, clock dividers
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and anything else associated with it. Any board that wants to use this
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framework needs to supply at least basic details of what is required.
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The core registers with drivers/cpufreq at init time if all the data
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necessary has been supplied.
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CPU support
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-----------
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The support for each CPU depends on the facilities provided by the
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SoC and the driver as each device has different PLL and clock chains
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associated with it.
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Slow Mode
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---------
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The SLOW mode where the PLL is turned off altogether and the
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system is fed by the external crystal input is currently not
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supported.
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sysfs
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-----
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The core code exports extra information via sysfs in the directory
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devices/system/cpu/cpu0/arch-freq.
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Board Support
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-------------
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Each board that wants to use the cpufreq code must register some basic
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information with the core driver to provide information about what the
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board requires and any restrictions being placed on it.
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The board needs to supply information about whether it needs the IO bank
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timings changing, any maximum frequency limits and information about the
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SDRAM refresh rate.
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Document Author
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---------------
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Ben Dooks, Copyright 2009 Simtec Electronics
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Licensed under GPLv2
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