Andrew Jeffery 8eb37aff76 pinctrl: aspeed-g5: Fix pin association of SPI1 function ... The SPI1 function was associated with the wrong pins: The functions that those pins provide is either an SPI debug or passthrough function coupled to SPI1. Make the SPI1 mux function configure the relevant pins and associate new SPI1DEBUG and SPI1PASSTHRU functions with the pins that were already defined. The notation used in the datasheet's multi-function pin table for the SoC is often creative: in this case the SYS* signals are enabled by a single bit, which is nothing unusual on its own, but in this case the bit was also participating in a multi-bit bitfield and therefore represented multiple functions. This fact was overlooked in the original patch. Fixes: 56e57cb6c0 (pinctrl: Add pinctrl-aspeed-g5 driver) Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>		2016-10-18 14:36:12 +02:00
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Kconfig	pinctrl: Add pinctrl-aspeed-g5 driver	2016-09-07 16:53:37 +02:00
Makefile	pinctrl: Add pinctrl-aspeed-g5 driver	2016-09-07 16:53:37 +02:00
pinctrl-aspeed-g4.c	pinctrl: Add pinctrl-aspeed-g4 driver	2016-09-07 16:51:49 +02:00
pinctrl-aspeed-g5.c	pinctrl: aspeed-g5: Fix pin association of SPI1 function	2016-10-18 14:36:12 +02:00
pinctrl-aspeed.c	pinctrl: aspeed: "Not enabled" is a significant mux state	2016-10-18 14:36:10 +02:00
pinctrl-aspeed.h	…