234 lines
5.1 KiB
C
234 lines
5.1 KiB
C
#ifndef ASM_X86__KVM_H
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#define ASM_X86__KVM_H
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/*
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* KVM x86 specific structures and definitions
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*
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*/
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#include <asm/types.h>
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#include <linux/ioctl.h>
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/* Architectural interrupt line count. */
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#define KVM_NR_INTERRUPTS 256
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struct kvm_memory_alias {
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__u32 slot; /* this has a different namespace than memory slots */
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__u32 flags;
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__u64 guest_phys_addr;
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__u64 memory_size;
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__u64 target_phys_addr;
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};
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/* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */
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struct kvm_pic_state {
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__u8 last_irr; /* edge detection */
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__u8 irr; /* interrupt request register */
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__u8 imr; /* interrupt mask register */
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__u8 isr; /* interrupt service register */
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__u8 priority_add; /* highest irq priority */
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__u8 irq_base;
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__u8 read_reg_select;
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__u8 poll;
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__u8 special_mask;
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__u8 init_state;
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__u8 auto_eoi;
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__u8 rotate_on_auto_eoi;
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__u8 special_fully_nested_mode;
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__u8 init4; /* true if 4 byte init */
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__u8 elcr; /* PIIX edge/trigger selection */
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__u8 elcr_mask;
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};
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#define KVM_IOAPIC_NUM_PINS 24
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struct kvm_ioapic_state {
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__u64 base_address;
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__u32 ioregsel;
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__u32 id;
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__u32 irr;
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__u32 pad;
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union {
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__u64 bits;
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struct {
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__u8 vector;
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__u8 delivery_mode:3;
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__u8 dest_mode:1;
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__u8 delivery_status:1;
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__u8 polarity:1;
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__u8 remote_irr:1;
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__u8 trig_mode:1;
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__u8 mask:1;
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__u8 reserve:7;
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__u8 reserved[4];
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__u8 dest_id;
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} fields;
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} redirtbl[KVM_IOAPIC_NUM_PINS];
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};
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#define KVM_IRQCHIP_PIC_MASTER 0
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#define KVM_IRQCHIP_PIC_SLAVE 1
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#define KVM_IRQCHIP_IOAPIC 2
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/* for KVM_GET_REGS and KVM_SET_REGS */
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struct kvm_regs {
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/* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
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__u64 rax, rbx, rcx, rdx;
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__u64 rsi, rdi, rsp, rbp;
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__u64 r8, r9, r10, r11;
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__u64 r12, r13, r14, r15;
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__u64 rip, rflags;
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};
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/* for KVM_GET_LAPIC and KVM_SET_LAPIC */
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#define KVM_APIC_REG_SIZE 0x400
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struct kvm_lapic_state {
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char regs[KVM_APIC_REG_SIZE];
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};
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struct kvm_segment {
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__u64 base;
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__u32 limit;
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__u16 selector;
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__u8 type;
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__u8 present, dpl, db, s, l, g, avl;
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__u8 unusable;
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__u8 padding;
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};
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struct kvm_dtable {
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__u64 base;
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__u16 limit;
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__u16 padding[3];
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};
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/* for KVM_GET_SREGS and KVM_SET_SREGS */
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struct kvm_sregs {
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/* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */
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struct kvm_segment cs, ds, es, fs, gs, ss;
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struct kvm_segment tr, ldt;
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struct kvm_dtable gdt, idt;
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__u64 cr0, cr2, cr3, cr4, cr8;
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__u64 efer;
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__u64 apic_base;
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__u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64];
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};
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/* for KVM_GET_FPU and KVM_SET_FPU */
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struct kvm_fpu {
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__u8 fpr[8][16];
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__u16 fcw;
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__u16 fsw;
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__u8 ftwx; /* in fxsave format */
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__u8 pad1;
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__u16 last_opcode;
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__u64 last_ip;
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__u64 last_dp;
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__u8 xmm[16][16];
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__u32 mxcsr;
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__u32 pad2;
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};
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struct kvm_msr_entry {
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__u32 index;
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__u32 reserved;
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__u64 data;
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};
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/* for KVM_GET_MSRS and KVM_SET_MSRS */
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struct kvm_msrs {
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__u32 nmsrs; /* number of msrs in entries */
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__u32 pad;
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struct kvm_msr_entry entries[0];
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};
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/* for KVM_GET_MSR_INDEX_LIST */
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struct kvm_msr_list {
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__u32 nmsrs; /* number of msrs in entries */
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__u32 indices[0];
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};
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struct kvm_cpuid_entry {
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__u32 function;
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__u32 eax;
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__u32 ebx;
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__u32 ecx;
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__u32 edx;
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__u32 padding;
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};
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/* for KVM_SET_CPUID */
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struct kvm_cpuid {
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__u32 nent;
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__u32 padding;
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struct kvm_cpuid_entry entries[0];
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};
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struct kvm_cpuid_entry2 {
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__u32 function;
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__u32 index;
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__u32 flags;
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__u32 eax;
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__u32 ebx;
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__u32 ecx;
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__u32 edx;
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__u32 padding[3];
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};
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#define KVM_CPUID_FLAG_SIGNIFCANT_INDEX 1
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#define KVM_CPUID_FLAG_STATEFUL_FUNC 2
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#define KVM_CPUID_FLAG_STATE_READ_NEXT 4
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/* for KVM_SET_CPUID2 */
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struct kvm_cpuid2 {
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__u32 nent;
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__u32 padding;
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struct kvm_cpuid_entry2 entries[0];
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};
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/* for KVM_GET_PIT and KVM_SET_PIT */
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struct kvm_pit_channel_state {
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__u32 count; /* can be 65536 */
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__u16 latched_count;
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__u8 count_latched;
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__u8 status_latched;
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__u8 status;
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__u8 read_state;
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__u8 write_state;
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__u8 write_latch;
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__u8 rw_mode;
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__u8 mode;
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__u8 bcd;
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__u8 gate;
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__s64 count_load_time;
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};
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struct kvm_pit_state {
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struct kvm_pit_channel_state channels[3];
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};
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#define KVM_TRC_INJ_VIRQ (KVM_TRC_HANDLER + 0x02)
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#define KVM_TRC_REDELIVER_EVT (KVM_TRC_HANDLER + 0x03)
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#define KVM_TRC_PEND_INTR (KVM_TRC_HANDLER + 0x04)
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#define KVM_TRC_IO_READ (KVM_TRC_HANDLER + 0x05)
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#define KVM_TRC_IO_WRITE (KVM_TRC_HANDLER + 0x06)
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#define KVM_TRC_CR_READ (KVM_TRC_HANDLER + 0x07)
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#define KVM_TRC_CR_WRITE (KVM_TRC_HANDLER + 0x08)
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#define KVM_TRC_DR_READ (KVM_TRC_HANDLER + 0x09)
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#define KVM_TRC_DR_WRITE (KVM_TRC_HANDLER + 0x0A)
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#define KVM_TRC_MSR_READ (KVM_TRC_HANDLER + 0x0B)
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#define KVM_TRC_MSR_WRITE (KVM_TRC_HANDLER + 0x0C)
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#define KVM_TRC_CPUID (KVM_TRC_HANDLER + 0x0D)
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#define KVM_TRC_INTR (KVM_TRC_HANDLER + 0x0E)
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#define KVM_TRC_NMI (KVM_TRC_HANDLER + 0x0F)
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#define KVM_TRC_VMMCALL (KVM_TRC_HANDLER + 0x10)
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#define KVM_TRC_HLT (KVM_TRC_HANDLER + 0x11)
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#define KVM_TRC_CLTS (KVM_TRC_HANDLER + 0x12)
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#define KVM_TRC_LMSW (KVM_TRC_HANDLER + 0x13)
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#define KVM_TRC_APIC_ACCESS (KVM_TRC_HANDLER + 0x14)
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#define KVM_TRC_TDP_FAULT (KVM_TRC_HANDLER + 0x15)
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#endif /* ASM_X86__KVM_H */
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