The two clock domains are enabled based on each input and output of the
chip being connected to its respective clock domain. The ASRC however
can bridge the two domains and as such can function as an input/output
to either domain. The hardware also requires that both clocks are
enabled before the ASRC is. Ensure these constraints by linking the
ASRCs to both SYSCLK and ASYNCCLK.
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
19c891924b